`书上说这是设计复杂状态机的方法，但是我分析一下，这种状态机设计的方法和一般用always和case设计的状态机的结果是不一样的，那么这种状态机有没有实际应用的价值，毕竟他和正常的状态机不一样，另外，是不是这个程序哪里不对呢？求大侠指点一二~
程序：
module fsm(inputclock,input reset,input a,output reg k2,output reg k1);
reg [1:0] state, nextstate;
parameter
idle = 2'b00,
start = 2'b01,
stop = 2'b10,
clear = 2'b11;
always @(posedgeclock)
begin
if(!reset)
state <= idle;
else
begin
state <= nextstate;
end
end
always @(stateor a)
case (state)
idle:if(a)
nextstate=start;
else
nextstate=idle;
start:if(a)
nextstate = start;
else
nextstate = stop;
stop:if(a)
nextstate = clear;
else
nextstate = stop;
clear: if(a)
nextstate = clear;
else
nextstate = idle;
defaultnextstate = 2'bxx;
endcase
always@(state,reset,a)
if(!reset) k1=0;
else
if (state == clear && !a)
k1=1;
else
k1 = 0;
always@(state,reset,a)
if(!reset) k2=0;
else
if (state == stop && a)
k2 = 1;
else k2 = 0;
endmodule
测试：
module test_fsm;
reg a;
reg clock,rst;
wire k2,k1;
initial
begin
a=0;
rst = 1;
clock = 0;
#22 rst = 0;
#133 rst = 1;
end
always #50 clock= ~clock;
always @(posedge clock)
begin
#30 a ={$random}%2;
#(3*50+12);
end
initial
begin
# 100000
$stop;
end
fsmm(clock,rst,a,k2,k1);
endmodule
`
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