module smg(a,seg,dig,clock);
input clock;
output [3:0] a;
output [7:0] seg; //数码管段码输出
output [3:0] dig; //数码管位码输出
reg [7:0] seg; //数码管段码输出寄存器
reg [3:0] disp_dat1; //显示数据寄存器
reg [3:0] disp_dat2; //显示数据寄存器
reg [3:0] disp_dat3; //显示数据寄存器
reg [3:0] disp_dat4; //显示数据寄存器
reg [3:0] disp_dat; //显示数据寄存器
reg [3:0] digt; //数码管位码输出寄存器
reg [3:0] a;
reg [16:0] data;
assign dig=~digt;
reg [36:0] count; //定义计数寄存器
reg [36:0] ct;
/*always@(posedge clock)*/
begin
disp_dat1<=data%10000/1000;
disp_dat2<=data%1000/100;
disp_dat3<=data%100/10;
disp_dat4<=data%10;
end
always@(posedge clock)
begin
count <= count + 1;
if (count==25'd25000)
begin
count<=0;
a=~a;
digt=(digt<<1);
if(digt==0)
digt=8'b0001;
end
end
always @ (digt)
begin
case (digt)
4'b1000 : disp_dat=disp_dat1;
4'b0100 : disp_dat=disp_dat2;
4'b0010 : disp_dat=disp_dat3;
4'b0001 : disp_dat=disp_dat4;
endcase
end
always @ (disp_dat)
begin
case (disp_dat)
4'd0 : seg = 8'hc0; //显示"0"
4'd1 : seg = 8'hf9; //显示"1"
4'd2 : seg = 8'ha4; //显示"2"
4'd3 : seg = 8'hb0; //显示"3"
4'd4 : seg = 8'h99; //显示"4"
4'd5 : seg = 8'h92; //显示"5"
4'd6 : seg = 8'h82; //显示"6"
4'd7 : seg = 8'hf8; //显示"7"
4'd8 : seg = 8'h80; //显示"8"
4'd9 : seg = 8'h90; //显示"9"
4'd10 : seg = 8'h7f; //显示"."
4'd11 : seg = 8'hff; //显示" "
endcase
end
always@(posedge clock)
begin
ct <= ct + 1;
if (ct==25'd250000)
begin
ct<=0;
data=data+1;
if(data==9999)
data<=0;
end
end
endmodule
module smg(a,seg,dig,clock);
input clock;
output [3:0] a;
output [7:0] seg; //数码管段码输出
output [3:0] dig; //数码管位码输出
reg [7:0] seg; //数码管段码输出寄存器
reg [3:0] disp_dat1; //显示数据寄存器
reg [3:0] disp_dat2; //显示数据寄存器
reg [3:0] disp_dat3; //显示数据寄存器
reg [3:0] disp_dat4; //显示数据寄存器
reg [3:0] disp_dat; //显示数据寄存器
reg [3:0] digt; //数码管位码输出寄存器
reg [3:0] a;
reg [16:0] data;
assign dig=~digt;
reg [36:0] count; //定义计数寄存器
reg [36:0] ct;
/*always@(posedge clock)*/
begin
disp_dat1<=data%10000/1000;
disp_dat2<=data%1000/100;
disp_dat3<=data%100/10;
disp_dat4<=data%10;
end
always@(posedge clock)
begin
count <= count + 1;
if (count==25'd25000)
begin
count<=0;
a=~a;
digt=(digt<<1);
if(digt==0)
digt=8'b0001;
end
end
always @ (digt)
begin
case (digt)
4'b1000 : disp_dat=disp_dat1;
4'b0100 : disp_dat=disp_dat2;
4'b0010 : disp_dat=disp_dat3;
4'b0001 : disp_dat=disp_dat4;
endcase
end
always @ (disp_dat)
begin
case (disp_dat)
4'd0 : seg = 8'hc0; //显示"0"
4'd1 : seg = 8'hf9; //显示"1"
4'd2 : seg = 8'ha4; //显示"2"
4'd3 : seg = 8'hb0; //显示"3"
4'd4 : seg = 8'h99; //显示"4"
4'd5 : seg = 8'h92; //显示"5"
4'd6 : seg = 8'h82; //显示"6"
4'd7 : seg = 8'hf8; //显示"7"
4'd8 : seg = 8'h80; //显示"8"
4'd9 : seg = 8'h90; //显示"9"
4'd10 : seg = 8'h7f; //显示"."
4'd11 : seg = 8'hff; //显示" "
endcase
end
always@(posedge clock)
begin
ct <= ct + 1;
if (ct==25'd250000)
begin
ct<=0;
data=data+1;
if(data==9999)
data<=0;
end
end
endmodule
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