VC707板上GTX物理分配有冲突

我尝试在VC707中做一个关于Aurora接口的原型设计。
我配置Aurora IP工作1通道单工模式，我计划将TX放在bank 119中，而将RX放在bank 118中。
我按照Xilinx提供的Aurora示例设计编写了我的Xdc文件。
合成后，我打开合成设计，在I / O规划中，我可以在E2中分配o_tx_p的串行引脚，而在F8中分配i_rx_p。
我检查了VC707的shcematic，我确信他们已成功分配到119和118银行。
但是，当我尝试将GTX参考时钟的引脚分配到bank 119（A10）和118（E10）时，Vivado总是禁止我这样做并向我显示一条消息作为附件，表示我有冲突。
但是，这没有意义。
在Xilinx的Aurora示例设计中，Xdc文件不限制GTX的引脚位置，但在综合和实现之后，反射时钟在右引脚中分配没有问题。
所以我很困惑为什么我的设计无法正常工作。
我想知道之前有没有人面对类似的问题？
这是什么意思？
提前致谢。



以下为原文

I try to do a prototype design in VC707 about Aurora interface. I configure the Aurora IP working 1 lane simplex mode, I plan to put the TX in bank 119 while RX in bank 118.

I follow the Aurora example design provided from Xilinx, to write my Xdc file. After synthesised, I open the synthesised design, in I/O planning, I can the serial pin of o_tx_p  is assigned in E2 while i_rx_p is assigned in F8. I checked the VC707 shcematic and I am sure they have been assigned in bank 119 and 118 sucessfully. However, when I try to assign the pin of GTX reference clock into bank 119 (A10) and 118 (E10), Vivado always forbid me to do that and show me a message as attachment, that said I have conflicts. However, this does not make sense.

In Aurora example design from Xilinx, the Xdc file does not constrain the pin location for GTX, but after synthesis and implementation, the refrernce clock is assigned in the right pins without problem. So I am confused why my design does not work as that.

I wonder does anyone confront the similar issue before? What does this mean?

Thanks in advance.