无法让SIM卡运行

谢谢florent  - 我明天会创建另一个帖子。
在原帖中查看解决方案



以下为原文

Thanks florent - I'll create the other thread tomorrow.
 
 
 
 
View solution in original post

你好@ john321
您正在关注哪个教程？
在此处分享教程链接。
谢谢，
维奈
--------------------------------------------------
------------------------------------------您是否尝试在Google中输入问题？
？
如果没有，你应该在发布之前。
此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。



以下为原文

Hi @john321
 
Which tutorial are you following?
Share the tutorial link here.
 
Thanks,
Vinay
--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

嗨Vuppala
对不起 - 这不会有帮助！
我正在做Vivado设计套件教程高级综合
UG871（v2017.1）2017年5月5日
这是PDF Vivado HLS首次启动时提出的第一个教程。
第1-8章很好。
第9章在IP Integrator中使用HLS IP
一切似乎工作正常，直到我到达最后一步，它需要
顶级模块名称，因此出错。
我试图手动插入我认为它可以使用但无济于事的东西。
我已经重复了上一章（RTL验证）并遵循了
如果应该留下一些东西，但也没有用。
从某种意义上来说它很好，因为它迫使我环顾四周
文件和界面更多，但如果我可以排序它会很好。
最后的第10步说运行行为模拟它出错了
由于缺少模块名称而无法运行，因此步骤11无法运行。
这可能是非常简单的事情 - 我还不够了解
发现我认为。
谢谢
学家



以下为原文

Hi Vuppala
 
Yes sorry - it would help wouldn't it!
 
I'm doing the Vivado Design Suite Tutorial High-level synthesis
UG871 (v2017.1) May 5 2017
This is the first tutorial PDF Vivado HLS brings up when first started.
 
Chapters 1-8 went fine.
 
Chapter 9  Using HLS IP in IP Integrator
Everything seems to work fine until I get to the final step and it requires
the top level module name and so errors out.
 
I've tried to manually insert what I think it could use but to no avail.
And I've repeated the previous chapter (RTL Verification) and followed
on in case that should have left something but that hasnt worked either.
 
In one respect its good because it has forced me to look around the
files and interface more but it would be good if I could sort it.
 
Step 10 at the end says to Run Behavioral Simulation which it errors
out on because of the lack of module name and so step 11 can't be run.
 
It might be something very simple - I just don't know enough yet to
spot it I think.
 
thanks
 
j.
 
 

我无法解决该教程的问题所以我已经转移到下一个（在同一个PDF中）Ch。
10在Zynq AP Soc设计中使用HLS IP。
这会产生相同的错误。
慢慢地看一遍，我注意到“创建HDL Wrapper”阶段（指令第4段）创建了包装文件，并将其放在文件夹名称“Non-Module Files（1）”下的sources窗格中。
这与教程中的屏幕捕获不符，后者将包装器直接放在Design Sources（2）下。
这可能是问题吗？
此外，我现在有一个错误列表，显示从Zynq_Design_Wrapper（8）开始的32个块设计错误
我可以在包装文件中看到... / bd / hdl文件夹。
谁能提出我在这里弄错了什么？
谢谢
学家



以下为原文

I can't resolve the issue with that tutorial so I've moved onto the next (in the same PDF) Ch. 10 Using HLS IP in a Zynq AP Soc design.
 
This produces the same error.
 
Going through this slowly I notice that the stage "Create HDL Wrapper" (instruction paragraph 4. ) creates the wrapper file and puts it in the sources pane under the folder name "Non-Module Files (1)"
 
This does not tally with the screen capture in the tutorial which puts the wrapper directly under Design Sources(2).
Could this be the issue?
 
Also I now  have an error listing showing 32 block design errors starting with the Zynq_Design_Wrapper (8)
I can see in the wrapper file itself in .../bd/hdl folder.
 
Can anyone suggest what I'm getting wrong here please?
 
thanks
 
j.