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马守川

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[问答]

求教FPGA时序约束问题与输入信号以及PLL输出Slack为负该如何解决?

Critical Warning: No exact pin location assignment(s) for 77 pins of 80 total pins
        Info: Pin addr_monitor[0] not assigned to an exact location on the device
        Info: Pin addr_monitor[2] not assigned to an exact location on the device
        Info: Pin addr_monitor[4] not assigned to an exact location on the device
        Info: Pin addr_monitor[6] not assigned to an exact location on the device
        Info: Pin addr_monitor[8] not assigned to an exact location on the device
        Info: Pin addr_monitor[10] not assigned to an exact location on the device
        Info: Pin addr_monitor[12] not assigned to an exact location on the device
        Info: Pin data_out[0] not assigned to an exact location on the device
        Info: Pin data_out[2] not assigned to an exact location on the device
        Info: Pin data_out[4] not assigned to an exact location on the device
        Info: Pin data_out[6] not assigned to an exact location on the device
        Info: Pin max[0] not assigned to an exact location on the device
        Info: Pin max[2] not assigned to an exact location on the device
        Info: Pin max[4] not assigned to an exact location on the device
        Info: Pin max[6] not assigned to an exact location on the device
        Info: Pin max[8] not assigned to an exact location on the device
        Info: Pin max[10] not assigned to an exact location on the device
        Info: Pin max[12] not assigned to an exact location on the device
        Info: Pin max[14] not assigned to an exact location on the device
        Info: Pin max[16] not assigned to an exact location on the device
        Info: Pin max[18] not assigned to an exact location on the device
        Info: Pin max[20] not assigned to an exact location on the device
        Info: Pin max[22] not assigned to an exact location on the device
        Info: Pin max[24] not assigned to an exact location on the device
        Info: Pin max[26] not assigned to an exact location on the device
        Info: Pin max[28] not assigned to an exact location on the device
        Info: Pin max[30] not assigned to an exact location on the device
        Info: Pin max[32] not assigned to an exact location on the device
        Info: Pin max[34] not assigned to an exact location on the device
        Info: Pin max[36] not assigned to an exact location on the device
        Info: Pin max[38] not assigned to an exact location on the device
        Info: Pin max[40] not assigned to an exact location on the device
        Info: Pin max[42] not assigned to an exact location on the device
        Info: Pin max[44] not assigned to an exact location on the device
        Info: Pin max[46] not assigned to an exact location on the device
        Info: Pin max[48] not assigned to an exact location on the device
        Info: Pin max[50] not assigned to an exact location on the device
        Info: Pin QUAN_SIG[0] not assigned to an exact location on the device
        Info: Pin stat_finish not assigned to an exact location on the device
        Info: Pin addr_monitor[1] not assigned to an exact location on the device
        Info: Pin addr_monitor[3] not assigned to an exact location on the device
        Info: Pin addr_monitor[5] not assigned to an exact location on the device
        Info: Pin addr_monitor[7] not assigned to an exact location on the device
        Info: Pin addr_monitor[9] not assigned to an exact location on the device
        Info: Pin addr_monitor[11] not assigned to an exact location on the device
        Info: Pin addr_monitor[13] not assigned to an exact location on the device
        Info: Pin data_out[1] not assigned to an exact location on the device
        Info: Pin data_out[3] not assigned to an exact location on the device
        Info: Pin data_out[5] not assigned to an exact location on the device
        Info: Pin data_out[7] not assigned to an exact location on the device
        Info: Pin max[1] not assigned to an exact location on the device
        Info: Pin max[3] not assigned to an exact location on the device
        Info: Pin max[5] not assigned to an exact location on the device
        Info: Pin max[7] not assigned to an exact location on the device
        Info: Pin max[9] not assigned to an exact location on the device
        Info: Pin max[11] not assigned to an exact location on the device
        Info: Pin max[13] not assigned to an exact location on the device
        Info: Pin max[15] not assigned to an exact location on the device
        Info: Pin max[17] not assigned to an exact location on the device
        Info: Pin max[19] not assigned to an exact location on the device
        Info: Pin max[21] not assigned to an exact location on the device
        Info: Pin max[23] not assigned to an exact location on the device
        Info: Pin max[25] not assigned to an exact location on the device
        Info: Pin max[27] not assigned to an exact location on the device
        Info: Pin max[29] not assigned to an exact location on the device
        Info: Pin max[31] not assigned to an exact location on the device
        Info: Pin max[33] not assigned to an exact location on the device
        Info: Pin max[35] not assigned to an exact location on the device
        Info: Pin max[37] not assigned to an exact location on the device
        Info: Pin max[39] not assigned to an exact location on the device
        Info: Pin max[41] not assigned to an exact location on the device
        Info: Pin max[43] not assigned to an exact location on the device
        Info: Pin max[45] not assigned to an exact location on the device
        Info: Pin max[47] not assigned to an exact location on the device
        Info: Pin max[49] not assigned to an exact location on the device
        Info: Pin max[51] not assigned to an exact location on the device
        Info: Pin QUAN_SIG[1] not assigned to an exact location on the device
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Fall) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
        Critical Warning: From pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) to pll_20MHz_inst|altpll_component|auto_generated|pll1|clk[1] (Rise) (setup and hold)
Critical Warning: Timing requirements not met


  • 4.png
  • 3.png
  • 2.png
  • 1.png

回帖(1)

卿小小_9e6

2020-4-29 17:56:54
01.引脚分配未完成,由此导致严重警告。
02.理论上讲,程序可以加载并运行(掩耳盗铃的方式,忽略警告)。
03.对于时序不满足要求的情况,建议尝试一下如下方式:即针对相位进行微调,调整数值和你设置的频率相关。
04.还有一种正规方式,分析时序报告,查看哪里不符合设计规范进行更改,如果还有警告,在*.sdc中加入时序优化指令(不是忽略指令)。这一点我不太会。
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  • Quartus-II_PLL_set.png

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