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74LS169 pdf datasheet
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2008-08-06
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54LS169/DM54LS169A/DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal
carry look-ahead for cascading in high-speed counting applications.
Synchronous operation is provided by having all
flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the countenable
inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four master-slave flip-flops
on the rising edge of the clock waveform.
This counter is fully programmable; that is, the outputs may
each be preset either high or low. The load input circuitry
allows loading with the carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level
at the load input disables the counter and causes the outputs
to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs (P and T) must be low to count.
The direction of the count is determined by the level of the
up/down input. When the input is high, the counter counts
up; when low, it counts down. Input T is fed forward to enable
the carry outputs. The carry output thus enabled will
produce a low-level output pulse with a duration approximately
equal to the high portion of the QA output when
counting up, and approximately equal to the low portion of
the QA output when counting down. This low-level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input. All inputs are diode
clamped to minimize transmission-line effects, thereby simplifying
system design.
This counter features a fully independent clock circuit.
Changes at control inputs (enable P, enable T, load, up/
down), which modify the operating mode, have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
Y Fully synchronous operation for counting and
programming.
Y Internal look-ahead for fast counting.
Y Carry output for n-bit cascading.
Y Fully independent clock circuit
Y Alternate Military/Aerospace device (54LS169) is
available. Contact a National Semiconductor Sales
Office/Distributor for specifications.
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal
carry look-ahead for cascading in high-speed counting applications.
Synchronous operation is provided by having all
flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the countenable
inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four master-slave flip-flops
on the rising edge of the clock waveform.
This counter is fully programmable; that is, the outputs may
each be preset either high or low. The load input circuitry
allows loading with the carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level
at the load input disables the counter and causes the outputs
to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs (P and T) must be low to count.
The direction of the count is determined by the level of the
up/down input. When the input is high, the counter counts
up; when low, it counts down. Input T is fed forward to enable
the carry outputs. The carry output thus enabled will
produce a low-level output pulse with a duration approximately
equal to the high portion of the QA output when
counting up, and approximately equal to the low portion of
the QA output when counting down. This low-level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input. All inputs are diode
clamped to minimize transmission-line effects, thereby simplifying
system design.
This counter features a fully independent clock circuit.
Changes at control inputs (enable P, enable T, load, up/
down), which modify the operating mode, have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
Y Fully synchronous operation for counting and
programming.
Y Internal look-ahead for fast counting.
Y Carry output for n-bit cascading.
Y Fully independent clock circuit
Y Alternate Military/Aerospace device (54LS169) is
available. Contact a National Semiconductor Sales
Office/Distributor for specifications.
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