这是一个实现4*4的键盘检测功能的程序，但是
仿真的时候前面一段出现了未知值，而且后面的有了些延迟，比如说行列分别是第二行第二列检测出零信号，但检测出来的却是第一行第二列有按键按下。
附有代码如下：
--分频器--这是一个6分频的分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
en
tity divider is
port(clk :in std_logic;
clk1kHZ :out std_logic
);
end divider;
architecture arch_divider of divider is
signal cnt :integer range 0 to 2:=0;--249999--
signal tmp_clk :std_logic :='0';
begin
process(clk)
begin
if(clk'event and clk='1') then
if(cnt=2) then
cnt<=0; tmp_clk<=not tmp_clk;
else cnt<=cnt+1;
end if;
end if;
end process;
clk1kHZ<=tmp_clk;
end arch_divider;
--0-3计数器--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
这是一个计数器，计1是第一行信号输出0，计2时第二行信号输出0，以此类推
entity counter is
port(clk:in std_logic;
output: out std_logic_vector(0 to 1));
end counter;
architecture arch_c of counter is
signal cnt:std_logic_vector(0 to 1):="00";
begin
process(clk)
begin
if(clk'event and clk='1') then
if(cnt="11") then cnt<="00";
else cnt<=cnt+1;
end if;
end if;
output<=cnt;
end process;
end arch_c;
--行信号输出--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scanin is
port(
countersign:in std_logic_vector(0 to 1);
outsign:out std_logic_vector(0 to 3));
end scanin;
architecture arch_si of scanin is
begin
process(countersign)
begin
case countersign is
when"00" => outsign<="1110";
when"01" => outsign<="1101";
when"10" => outsign<="1011";
when"11" => outsign<="0111";
when others => null;
end case;
end process;
end arch_si;
--列信号读入--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scanout is
port(clk:in std_logic;
countersign:in std_logic_vector(0 to 1);
input:in std_logic_vector(0 to 3);
output:out std_logic_vector(0 to 3));
end scanout;
architecture arch_so of scanout is
begin
process
begin
wait until falling_edge(clk);
case countersign is
when"00"=> case input is
when"1110" => output<="0000";
when"1101" => output<="0001";
when"1011" => output<="0010";
when"0111" => output<="0011";
when others=>null;
end case;
when"01"=> case input is
when"1110" => output<="0100";
when"1101" => output<="0101";
when"1011" => output<="0110";
when"0111" => output<="0111";
when others=>null;
end case;
when"10"=> case input is
when"1110" => output<="1000";
when"1101" => output<="1001";
when"1011" => output<="1010";
when"0111" => output<="1011";
when others=>null;
end case;
when"11"=> case input is
when"1110" => output<="1100";
when"1101" => output<="1101";
when"1011" => output<="1110";
when"0111" => output<="1111";
when others=>null;
end case;
when others=>null;
end case;
end process;
end arch_so;
--47译码器--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder47 is
port(input:in std_logic_vector(0 to 3);
abcdefg:out std_logic_vector(0 to 6));
end decoder47;
architecture arch_d of decoder47 is
begin
process(input)
begin
case input is
when "0000" => abcdefg<="1001111";--显示1--
when "0001" => abcdefg<="0010010";--显示2--
when "0010" => abcdefg<="0000110";--显示3--
when "0011" => abcdefg<="0001000";--显示A--
when "0100" => abcdefg<="1001100";--显示4--
when "0101" => abcdefg<="0100100";--显示5--
when "0110" => abcdefg<="0100000";--显示6--
when "0111" => abcdefg<="1100000";--显示B--
when "1000" => abcdefg<="0001111";--显示7--
when "1001" => abcdefg<="0000000";--显示8--
when "1010" => abcdefg<="0000100";--显示9--
when "1011" => abcdefg<="0110001";--显示C--
when "1100" => abcdefg<="0111000";--显示F--
when "1101" => abcdefg<="0000001";--显示0--
when "1110" => abcdefg<="0110000";--显示E--
when "1111" => abcdefg<="1000010";--显示D--
when others => null;
end case;
end process;
end arch_d;
