谢谢你的信息，但是当我拿到起动器套件时，我已经读完了那份文件。还有一些错误信息：2.1.4“当安装JP17跳线时，引脚1必须连接到引脚3，引脚2必须连接到引脚4。”它正确地说明如何在第38页上安装跳线。不管怎样，当我尝试时，调试器不能正常工作。我设置了断点，我知道PIC已经停止（通过我的代码中的LED指示），但是调试器从来没有说过它在断点处停止了！如果我暂停PIC，它永远不会告诉我它停在哪里，我不能读取任何实际的变量值。我做错什么了？在我的PrimaMac配置中有什么不对吗？
以上来自于百度翻译
以下为原文
Thanks for the info, but I've read through that document when I got the Starter Kit. There's also some wrong information:
2.1.4 "When the JP17 jumper is installed, pin 1 must be connected to pin 3, and pin 2 must be connected to pin 4." is wrong. It correctly states how to install the jumper on page 38.
Anyway, the debugger won't work right when I try it. I set a breakpoint and I know that the PIC has stopped (by LED indications from my code), but the debugger never says that it stopped at the breakpoint! If I pause the PIC, it never tells me where it stopped and I can't read any actual variable values. What am I doing wrong?
Do I have something wrong in my #pragma configs?
/*** DEVCFG0 ***/
#pragma config DEBUG = ON // Background Debugger Enable (Debugger is enabled)
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2) - 2 allows debugging
#pragma config TRCEN = OFF // Trace Enable (Trace features in the CPU are disabled)
#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = PG_ALL // Debug Mode CPU Access Permission (Allow CPU access to all permission regions)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
#pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)
#pragma config CP = OFF // Code Protect (Protection Disabled)
/*** DEVCFG1 ***/
#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = ON // Secondary Oscillator Enable (Enable SOSC)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = EC // Primary Oscillator Configuration (External clock mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Disabled, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)
/*** DEVCFG2 ***/
// Clock frequency is 24MHz, driven by either an oscillator or a crystal.
// The 24MHz input will divided by the setting of FPLLIDIV (3).
// Set FPLLRNG to match the range of the divided frequency (5-10MHz).
// The divided input will be multiplied by the FPLLMULT setting (50).
// The final system clock value is the result of division by FPLLODIV (2).
//
// System clock formula:
//
// Fsys = Posc / FPLLIDIV x FPLLMULT / FPLLODIV
//
#pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)
#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
#pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)
#pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
#pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
#pragma config VBATBOREN = ON // Enable ZPBOR during VBAT Mode
#pragma config DSBOREN = ON // Enable ZPBOR during Deep Sleep Mode
#pragma config DSWDTPS = DSPS32 // Deep Sleep Watchdog Timer Postscaler 1:2^36
#pragma config DSWDTOSC = LPRC // Select LPRC as DSWDT Reference clock
#pragma config DSWDTEN = OFF // Disable DSWDT during Deep Sleep Mode
#pragma config FDSEN = ON // Disable DSEN bit in DSCON
#pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)
/*** DEVCFG3 ***/
#pragma config USERID = 0xffff // Set the User ID (0x0 to 0xffff)
#pragma config EXTDDRSIZE = DDR_SIZE_128MB // External DDR2 Size is 128 MB
#pragma config FMIIEN = OFF // Ethernet RMII/MII Enable (RMII Enabled)
#pragma config FETHIO = ON // Ethernet I/O Pin Select (Alternate Ethernet I/O)
#pragma config PGL1WAY = OFF // Permission Group Lock One Way Configuration (Allow multiple reconfigurations)
#pragma config PMDL1WAY = OFF // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
#pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
/*** DEVCFG4 ***/
#pragma config SWDTPS = SPS1048576 // Sleep Mode Watchdog Timer Postscaler
/*** BF1SEQ0 ***/
#pragma config TSEQ = 0x0000 // Boot Flash True Sequence Number
#pragma config CSEQ = 0xffff // Boot Flash Complement Sequence Number
谢谢你的信息，但是当我拿到起动器套件时，我已经读完了那份文件。还有一些错误信息：2.1.4“当安装JP17跳线时，引脚1必须连接到引脚3，引脚2必须连接到引脚4。”它正确地说明如何在第38页上安装跳线。不管怎样，当我尝试时，调试器不能正常工作。我设置了断点，我知道PIC已经停止（通过我的代码中的LED指示），但是调试器从来没有说过它在断点处停止了！如果我暂停PIC，它永远不会告诉我它停在哪里，我不能读取任何实际的变量值。我做错什么了？在我的PrimaMac配置中有什么不对吗？
以上来自于百度翻译
以下为原文
Thanks for the info, but I've read through that document when I got the Starter Kit. There's also some wrong information:
2.1.4 "When the JP17 jumper is installed, pin 1 must be connected to pin 3, and pin 2 must be connected to pin 4." is wrong. It correctly states how to install the jumper on page 38.
Anyway, the debugger won't work right when I try it. I set a breakpoint and I know that the PIC has stopped (by LED indications from my code), but the debugger never says that it stopped at the breakpoint! If I pause the PIC, it never tells me where it stopped and I can't read any actual variable values. What am I doing wrong?
Do I have something wrong in my #pragma configs?
/*** DEVCFG0 ***/
#pragma config DEBUG = ON // Background Debugger Enable (Debugger is enabled)
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2) - 2 allows debugging
#pragma config TRCEN = OFF // Trace Enable (Trace features in the CPU are disabled)
#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = PG_ALL // Debug Mode CPU Access Permission (Allow CPU access to all permission regions)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
#pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)
#pragma config CP = OFF // Code Protect (Protection Disabled)
/*** DEVCFG1 ***/
#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = ON // Secondary Oscillator Enable (Enable SOSC)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = EC // Primary Oscillator Configuration (External clock mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Disabled, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)
/*** DEVCFG2 ***/
// Clock frequency is 24MHz, driven by either an oscillator or a crystal.
// The 24MHz input will divided by the setting of FPLLIDIV (3).
// Set FPLLRNG to match the range of the divided frequency (5-10MHz).
// The divided input will be multiplied by the FPLLMULT setting (50).
// The final system clock value is the result of division by FPLLODIV (2).
//
// System clock formula:
//
// Fsys = Posc / FPLLIDIV x FPLLMULT / FPLLODIV
//
#pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)
#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
#pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)
#pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
#pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
#pragma config VBATBOREN = ON // Enable ZPBOR during VBAT Mode
#pragma config DSBOREN = ON // Enable ZPBOR during Deep Sleep Mode
#pragma config DSWDTPS = DSPS32 // Deep Sleep Watchdog Timer Postscaler 1:2^36
#pragma config DSWDTOSC = LPRC // Select LPRC as DSWDT Reference clock
#pragma config DSWDTEN = OFF // Disable DSWDT during Deep Sleep Mode
#pragma config FDSEN = ON // Disable DSEN bit in DSCON
#pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)
/*** DEVCFG3 ***/
#pragma config USERID = 0xffff // Set the User ID (0x0 to 0xffff)
#pragma config EXTDDRSIZE = DDR_SIZE_128MB // External DDR2 Size is 128 MB
#pragma config FMIIEN = OFF // Ethernet RMII/MII Enable (RMII Enabled)
#pragma config FETHIO = ON // Ethernet I/O Pin Select (Alternate Ethernet I/O)
#pragma config PGL1WAY = OFF // Permission Group Lock One Way Configuration (Allow multiple reconfigurations)
#pragma config PMDL1WAY = OFF // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
#pragma config IOL1WAY = OFF // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
/*** DEVCFG4 ***/
#pragma config SWDTPS = SPS1048576 // Sleep Mode Watchdog Timer Postscaler
/*** BF1SEQ0 ***/
#pragma config TSEQ = 0x0000 // Boot Flash True Sequence Number
#pragma config CSEQ = 0xffff // Boot Flash Complement Sequence Number
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