FIFOout组件是否可用？

没有FIFOUT组件。我理解挫折开始UDB设计。通常，UDB不需要并行输入。你能描述一下你想达到什么目的来进一步建议你吗？
奥迪赛1



     以下为原文
  There is no FIFOout component. I understand frustration starting UDB design. Typically parallel input is not required for UDB. Can you describe what you trying to accomplish to further advise you?
odissey1

目标是用FPGA来回传送好大小的数据块。
我注意到的第一件事是外部存储器接口组件。他们看起来很理想，直到我注意到他们的公共汽车钟最大是33兆赫。
因为在FPGA方面有很大的灵活性，所以我决定我可以“滚我自己”的界面。这将避免拖垮整个总线时钟，并可能使时钟与其他模块混淆。我认为16位FIFOIN和FIFOUT与DMA和一点胶水逻辑将是解决方案。不幸的是，我没有意识到获得一个工作的先进先出的范围。
然后，我认为8位FIFOIN和8位控制寄存器与DMA可能是足够的。DMA效率低，但很可能仍然能完成任务。在这种情况下，我不知道什么时候用新的字节更新控制寄存器，所以我不能得到一个可用的写信号到FPGA。



     以下为原文
  The goal is to transfer good size blocks of data back and forth with an FPGA.
 
The first thing I noticed was the external memory interface components.  They seemed ideal until I noticed their bus clock maximum is 33Mhz.
 
Since there is great flexibility on the FPGA side, I decided I could "roll my own" interface.  This would avoid dragging down the whole bus clock and possibly messing with the clocks to my other modules.  I thought 16 bit FIFOin and FIFOout with DMA and a bit of glue logic would be the solution.  Unfortunately, I didn't realized the scope of getting a working FIFOout.
 
Then I thought 8 bit FIFOin and 8 bit control register out with DMA might be adequate.  The DMA would be less efficient, but would probably still get the job done.  In this scenario, I don't know when the control register is updated with a new byte, so I can't get a usable write signal to the FPGA.

我仅次于你的感情。我已经在一些PSoC项目上辛辛苦苦地工作，以绕过GPP对FPGA的GoFIFO支持的缺失。



     以下为原文
  I second your sentiment.  I've worked really hard on a few PSOC projects to get around the lack of goof fifo support form GPP to FPGA and back.

没有FIFOOUT组件，如果您的需求是FIFO内容的并行输出，这是不可能的直接与UDBs，但是您可以有一个并行输出的累加器从默认实例的数据通路，你应该实例化CypPSo33DP，同时选择数据路径。
如果你打算使用DMAS，你可以把内容传送到FIFO，把它推到累加器中的一个数据通路状态，输出将被驱动在并行输出上。
我附上了一个组件，我用一个计数器的16位并行输出来开发它。请注意，这只是为了您的参考，可能不是生产准备好的。
计数器042V4.ZIP
3兆字节



     以下为原文
  There is no FIFOout component , If your requirement is a parallel output of FIFO content, this is not possible with directly with UDBs however you can have a parallel output of the accumulator from the default instance of the datapath, you should instantiate cy_psoc3_dp while selecting the datapath.
 
 
And if you are planning to use DMAs you can transfer content to FIFO, push it into Accumulator in one of the state of datapath , the output will be driven on the parallel output.
 
 
I'm attaching a component that I developed some time back with 16bit parallel output of a counter .Please note that this is just for your reference and may not be production ready.

•   Counter_042_V4.zip 3.0 MB