mipi-csi2-rx示例设计许可证错误

您好@sridhargunnam，
我确认您需要以下许可证（所有许可证均可用作硬件评估或免费（TPG）许可证）：
-  MIPI CSI2
-  VPSS
-  HDMI
-  MIPI DSI TX
-  TPG
我写了AR＃70308（可能在几天后在线）来捕获这些信息。
请注意，您不需要HDMI许可证即可构建BD，因此您可以在生成比特流之前生成并删除HDMI IP。
如果您使用的是Windows操作系统：
确保使用非常短的路径。
否则，您可能会看到GAMMA LUT和Demosaic IP的错误。
我所做的是生成BD然后以非常短的名称保存项目（我在我的C：驱动器下直接使用了项目名称“X”）
在使用硬件评估许可证时，您应该看到AR＃70165（也适用于MIPI子系统）
如果在这个问题上一切都很清楚，请将响应标记为关闭线程的解决方案。
最好的祝福，
弗洛朗
产品应用工程师 - 视频和嵌入式
FlorentProduct应用工程师 -  Xilinx技术支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。
在原帖中查看解决方案



以下为原文

Hi @sridhargunnam,
 
I confirmed that you need the following licenses (all available as Hardware Evaluation or free (TPG) licenses):
- MIPI CSI2
- VPSS
- HDMI
- MIPI DSI TX
- TPG
 
I have written AR#70308 (might be online in few days) to capture this information.
 
Note that you don't need the HDMI license to build the BD, so you can generate it and remove the HDMI IP before generating the bitstream.
 
If you are using windows OS:

• Make sure you are using a very short path. Else you might see error with the GAMMA LUT and Demosaic IP. What I have done is to generate the BD and then save the project as with a very short name (I have used project name "X" directly under my C: drive)
  
• As you are using a Hardware Evaluation license, you should see AR#70165 (also valid for the MIPI Subsystems)
  

If everything is clear for you on this subject, please kindly mark a response as solution to close the thread.
 
Best Regards,
 
Florent
Product Application Engineer - Video and Embedded
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
View solution in original post

@sridhargunnam
您可以在tcl控制台中运行以下命令，并确保所有IP都是最新的：
report_ip_status
如果未更新IP，请在tcl控制台中运行以下命令：
upgrade_ip [get_ips]
问候
罗希特
--------------------------------------------------
--------------------------------------------请注意 - 请注明
如果提供的信息有用，请回答“接受为解决方案”。
将Kudos发送给您认为有用且回复的帖子.------------------------------------
--------------------------------------------------
--------
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
----------------------



以下为原文

@sridhargunnam
 
Can you run the below command in the tcl console and make sure all the IPs are up to date:
report_ip_status
 
If IPs are not updated, run the below command in the tcl console:
upgrade_ip [get_ips]
 
Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
 
Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

None


以下为原文

Thanks for the reply.
 
The IP are up to date. Do you think there any other issues? 
 
One thing I observed is that when customizing the IP, I didn't see the tab for board, which is present in the figures shown in the documentation. Please find them in the attachments. 
 
I was trying to use mipi_csi2_rx with IMX274 camera sensor. I instantiated the IP in vivado, did "generate output products", then tried to open the example design project, as I am unsure of all the connections to this IP block. Do you think there is a better way to use these IP's? The mipi_csi2_rx IP documentation is not clear on how to build example design. 
 
 
report_ip_status 
-------------------------------------------------------------------------------------------------------------------------------------------------------------
IP Status Summary
1. Project IP Status
--------------------
Your project uses 12 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.
More information on the Xilinx versioning policy is available at www.xilinx.com.
Project IP Instances
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_subsystem_0 | Up-to-date | No changes required | *(1) | MIPI CSI-2 Rx | 3.0 | 3.0 | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Subsystem | | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0 | Up-to-date | No changes required | *(2) | MIPI D-PHY | 4.0 | 4.0 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_r_sync_0 | Up-to-date | No changes required | *(3) | Processor System | 5.0 | 5.0 (Rev. 12) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Reset | (Rev. | | | |
| | | | | | 12) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_rx_0 | Up-to-date | No changes required | *(4) | MIPI CSI-2 Rx | 1.0 | 1.0 (Rev. 6) | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Controller | (Rev. | | | |
| | | | | | 6) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0 | Up-to-date | No changes required | Change | Video Format | 1.0 | 1.0 (Rev. 8) | Included | xczu9eg-ffvb1156-2-e |
| | | | Log not | Bridge | (Rev. | | | |
| | | | available | | 8) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0_hssio_rx | Up-to-date | No changes required | *(5) | High Speed | 3.2 | 3.2 (Rev. 2) | Included | xczu9eg-ffvb1156-2-e |
| | | | | SelectIO Wizard | (Rev. | | | |
| | | | | | 2) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_axis_converter | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Width Converter | (Rev. | | | |
| | | | | | 13) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_fifo | Up-to-date | No changes required | *(7) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fc_322048 | Up-to-date | No changes required | *(8) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo0 | Up-to-date | No changes required | *(9) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo1 | Up-to-date | No changes required | *(10) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo2 | Up-to-date | No changes required | *(11) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_subsystem_v3_0/doc/mipi_csi2_rx_subsystem_v3_0_changelog.txt
*(2) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_dphy_v4_0/doc/mipi_dphy_v4_0_changelog.txt
*(3) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(4) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_ctrl_v1_0/doc/mipi_csi2_rx_ctrl_v1_0_changelog.txt
*(5) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/high_speed_selectio_wiz_v3_2/doc/high_speed_selectio_wiz_v3_2_changelog.txt
*(6) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_dwidth_converter_v1_1/doc/axis_dwidth_converter_v1_1_changelog.txt
*(7) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(8) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(9) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(10) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(11) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
-------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 
Below is the log for update_ip command:
 
upgrade_ip [get_ips mipi_*]
WARNING: [Coretcl 2-1042] No IP was identified for upgrade.
 

关于我得到的错误的一些额外信息。
当我为MIPI_CSI2_RX_subsystem打开示例IP设计时，我得到了缺少块的以下设计。
你能帮我怎么办吗？
谢谢，
斯里达尔



以下为原文

Some extra information on the error I am getting. 
 
When I open example IP Design for MIPI_CSI2_RX_subsystem, I get following design with missing blocks. Can you help me how to proceed? 
 
Thanks, 
Sridhar