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[问答]

如何在SPARTAN 6 phy的GEN1和GEN2时钟生成之间切换

嗨,
我的名字是dasarath,
我正在将Spartan 6 phy集成到SATA(Tp + Link + Mac图层)Gen 2 for HOST。
根据SATA协议,完成的OOB是GEN 1,并以协商的速度重置事物。
例如,如果设备支持GEN2,如果设备支持GEN2,则在GEN1完成的GEN2 phyob将在GEN 2成功进行协商,如果设备仅支持GEN1,则应在GEN1成功进行速度协商。
在Virtex 6中,我发现TXRATE和RXRATE端口,为这些端口驱动适当的值,能够生成GEN1和GEN2时钟。
斯巴达6中有这样的港口吗?
如果不是,我们如何在SPARTAN 6 phy的GEN1和GEN2时钟生成之间切换。
请支持我。
感谢您,
问候
P Dasarath

以上来自于谷歌翻译


以下为原文

Hi,
My name is dasarath,

I am integrating the Spartan 6 phy to SATA ( Tp+Link+Mac layers) Gen 2 for HOST.
As per SATA protocol OOB done is GEN 1 and reset of things done at negotiated speed. for example for GEN2 phy oob done at GEN1 speed and speed negotiation should be successful at GEN  2 if  device supports GEN2, if device supports only GEN1 speed negotaition should be successful at GEN1.

In Virtex 6 i found ports TXRATE and RXRATE, driving proper values to these ports phy able to generate the GEN1 and GEN2 clocks.
Is there such ports in spartan 6?
If no, How can we switch between GEN1 and GEN2 clock generation for SPARTAN 6 phy.

Kindly support me .

Thanking you,

regards
P Dasarath

回帖(4)

贾佳斌

2019-7-24 09:51:29
您需要通过DRP控制PLL_TXDIVSEL_OUT和PLL_RXDIVSEL_OUT属性。请在通过DRP更新这些参数后应用GTPRESET。
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----------------------------别忘了回复,给予kudo并接受为解决方案---------
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以上来自于谷歌翻译


以下为原文

You will need to control PLL_TXDIVSEL_OUT and PLL_RXDIVSEL_OUT attributes through DRP.

Please apply a GTPRESET after updating these parameters through DRP.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
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康沧鹤

2019-7-24 10:05:37
要驱动DRP端口,我们是否需要开发自定义块,或者我们可以通过coregen生成。
您能否为DRP端口提供时序图(DRP读写)的数据或链接。

以上来自于谷歌翻译


以下为原文

To drive the DRP ports, Do we need to develope the custom block or we can generate through the coregen.
 
Can you provide the doucument or link for timing diagrams(read and write on DRP) of this DRP ports.
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李华瑞

2019-7-24 10:25:11
由于未知原因,我没有设法让Gen1在Spartan6中工作。
Gen2工作得很好。
选择Core2中的SATA2用于Gen2 SATA实现。

以上来自于谷歌翻译


以下为原文

I didn't manage to make Gen1 work in Spartan6 for unknown reasons. Gen2 works fine though. Choose SATA2 in core gen for Gen2 SATA impelementation.
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康沧鹤

2019-7-24 10:41:30
我的主人应该支持GEN1和GEN2。
当在Gen1进行速度协商时,phy必须生成GEN1时钟和
当在Gen2进行速度协商时,phy必须生成GEN2时钟。
在virtex6板上,有端口级支持,但对于仅通过DRP端口的spartan 6,我们可以配置PHY。
那么有没有现成的代码可用于驱动DRP端口,或者我们可以从coregen生成。

以上来自于谷歌翻译


以下为原文

My host supposed to support GEN1 and  GEN2.
 
when speed negotiation is done at Gen1, the phy has to generate the GEN1 clocks and
 
When speed negotiation is done at Gen2, the phy has to generate the GEN2 clocks.
 
In virtex6 board for this, there is port level support, But for spartan 6 only through DRP ports the we can configure the PHY.
 
So is there any readymade code available for driving the DRP ports or we can generate from the coregen .
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