用于FPGA的xilinx gtx phy是否支持SSC时钟？

喜
我为pcie gen1 ops配置了V6 gtx phy，并且运行良好。
然而，我设置phy的方式是它使用板载100M osc。
作为refclk，它使用这个100M clk进入FPGA PLL来获得pcie pipe_clk（125MHz）。
这个方案对我来说很好。
和pcie链接很好。
然而，当我更改phy以使用来自pcie插槽本身的100M refclk时，系统不起作用，即不会发生pcie链接。
我已经检查过，我有正确的引脚从pcie插槽中点击100M refclk。
我的问题 -
1）用于FPGA的xilinx gtx phy是否支持SSC时钟？
2）如果我在主机端启用或取消了SSC时钟，那么我需要在gtx phy中处理所有参数吗？
3）当我使用onchip 100M osc来获取refclk但是当我使用来自pcie插槽的时钟时，fpga设置可靠地工作的任何指针？
任何有指针的pcie + fpga大师？
帮助非常感谢...
谢谢，
ž。



以下为原文

hi,

i have configured the V6 gtx phy for pcie gen1 ops and its working well. however the way i've setup the phy is that it uses an onboard 100M osc. as refclk and it uses this 100M clk going into the fpga PLL to get the pcie pipe_clk (125MHz).

this scheme works fine for me. and pcie link up is good.

however when i change the phy to use the 100M refclk from the pcie slot itself, the system does not work, i.e. the pcie link up does not happen. i've checked and i have the correct pins to tap the 100M refclk from the pcie slot.

my questions -
1) does the xilinx gtx phy for FPGA support SSC clock?
2) if I have the SSC clock enabled or di***aled on the host side, what all parameters do i need to take care of in the gtx phy?
3) any pointers as to why the fpga setup works reliably when i use the onchip 100M osc to derive the refclk but does not work when i use the clock from the pcie slot?

any pcie+fpga gurus with pointers? help is greately appreciated ...

thanks,

z.