UART参考设计，Xilinx提供 (VHDL)
DISCLAIMER ****************************************************************************************************************************************** THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANtiES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. ****************************************************************************************************************************************** File Contents ****************************************************************************************************************************************** This zip file contains the following folders: vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd. ****************************************************************************************************************************************** Design Notes ****************************************************************************************************************************************** The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. Complete documentation for the design can be found in XAPP341 available for download from the Xilinx website. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device. Please also note that this design has been verified through simulations, but not on actual hardware. ****************************************************************************************************************************************** Technical Support ****************************************************************************************************************************************** Technical support for this design and any other CoolRunner CPLD issues can be obtained as follows: North American Support
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