EDIF网表实施错误

您好
我有一个模块的EDIF网表（由Vivado 2017.4中的第3方生成）。
我没有模块源verilog。
我有加密模块的行为模型，我有一个行为模型的测试平台。
行为模拟在Modelsim中运行。
行为模型为Modelsim提供了预编译的库。
我想用“结构”模型替换行为模型，我认为我可以通过“实现”在Vivado中生成
Vivado中的EDIF网表，并为Modelsim仿真编译输出。
所以我打开了一个带有EDIF网表的项目，并尝试通过实施来运行它。
我似乎无法在Viviado中实现EDIF
a）为所有端口（大多数不是顶级IO端口）生成IBUF和OBUF，并快速耗尽所选设备的IO
b）正在为未放置的顶级端口生成错误。
有没有办法绕过I / O BUF分配并避免与未放置的顶级IO相关的错误。
我已经附加了实现日志文件。
谢谢
财务巴雷
error_log.txt 20 KB



以下为原文

HI
I have an EDIF netlist (generated by 3'rd party in Vivado 2017.4) for a module. I do not have the the module source verilog.
I have behavioral model for the module which is encrypted and I have a testbench for the behavioral model.
The behavioral simulation is run in Modelsim.  
The behavioral model is given a pre-compiled library for Modelsim.

I wanted to replace the behavioral model with "structural" model which I thought I could generate in Vivado by "implementing"
the EDIF netlist in Vivado and compiling the output for Modelsim simulation.

So I opened a project with the EDIF netlist in it and attempted to run this through implementation.

I do not appear to be able to implement the EDIF in Viviado as it is
a) Generating IBUF's and OBUF's for all ports (most of which are not Top level IO ports) and quickly runs out of IO for the selected device
b) is generating errors for top level ports which are not placed.

Is there a way of bypassing the I/O BUF assignments and avoiding errors associated with unplaced top level IO.

I have attached the implementation log file.

Thanks
Finbarr
            error_log.txt ‏20 KB