ISE 14.7优化完全不相关的信号

我正致力于Virtex-6设计的时序收敛（使用ISE 14.7）。
我面临着一个奇怪的问题，ISE显然将一些完全不相关的逻辑合并在一起（信号甚至不在相同的时钟频率上运行）。
我已经设置了以下选项（适用于Synthesis和MAP / PAR），以避免优化不相关的信号：
-  resource_sharing off
-  ignore_keep_hierarchy off
-  LUT结合起来
MAP和Synthesis的Optmization设置为“Speed”。
-keep_hierarchy设置为“Soft”，-hetlist_hierarchy设置为“Rebuilt”。
我厌倦了-keep_hierarchy“是”的合成，但如果我这样做，我会遇到大量的映射器错误消息。
附上你可以找到时间报告。
失败路径在11954行。信号“../fmc_raw_dat_dff_s”与所有“../inst_tmem_user/ ..”信号位于不同的时钟域上，并且它们不必彼此做任何事情。
“../inst_tmem_user / ..”中的信号与配置寄存器组相关，“fmc_raw_dat_dff_s”信号是ADC输入后直接与寄存器组无连接的流水线级（它不可配置且具有
没有来自寄存器库或类似物的运行时钟启用）。
这条道路上的可疑网名如“lut77809_42134”也引起了我的注意。
没有使用“人类可读”名称这一事实指出该工具将不同的逻辑优化在一起，因此它无法分配可读的名称（因为我的VHDL源中没有这样的信号）。
有人知道这个（或类似的）问题吗？
有什么建议我可以试试吗？



以下为原文

I am working on timing-closure for a Virtex-6 Design (using ISE 14.7). I am facing the strange issue that ISE is obviously merging some logic together that is completely unrelated (the signals do not even run on the same clock frequency).

I already set the following options (for Synthesis and MAP/PAR where applicable) to avoid optimization of signals that are not related:
- resource_sharing off
- ignore_keep_hierarchy off
- LUT Combining off

Optmization of MAP and Synthesis is set to "Speed".
-keep_hierarchy is set to "Soft" and -hetlist_hierarchy to "Rebuilt".

I tired synthesyzing with -keep_hierarchy "Yes" but I run into tons of mapper error messages if I do so.

Attached you can find the timing report. The failing path is on line 11954. The signal "../fmc_raw_dat_dff_s" is on a different clock domain than all the "../inst_tmem_user/.." signals and they do not have to do anything with each other. The signals in "../inst_tmem_user/.." are related to the register bank for configuration, the "fmc_raw_dat_dff_s" signal is a pipeline stage directly after the ADC input that has no connections to the register bank (it is not configurable and has no runtime-clock enable from the register bank or anything similar).

The suspicious net-names like "lut77809_42134" for this path also catched my attention. The fact that no "human readable" names are used points into the directon that the tool optimizes different logic together and hence it cannot assign a readable name (because no such signal is present in my VHDL sources).

Does anybody know this (or a similar) problem? Any suggestions what I could try?