为什么短负荷不在史密斯圆图的短路点？

> {quote：title = Jiyuan写道：} {quote}> SOLT校准后，我将短负载连接到一个端口。
阻抗点不在S11史密斯圆图的短路点上，而是旋转一定程度。
开放负载也是如此。
但它们的相位差是180度。
为什么？
你没有说你使用的是哪种VNA或校准套件，这通常很有用，但在这种情况下它并不重要。
这里有几件事。
1）“短”实际上是“抵消短”。
它是一个传输线，阻抗Zo通常为50欧姆，有些长度 - 通常为几毫米，但由HP / Agilent表示为ps的延迟。
（Rohde和Schwarz相比之下表达了他们的延迟mm）。
不能期望这种偏移短路表现得像理想的短路。
2）短路有一些电感。
它通常可以忽略不计，但同样会使点在史密斯圆图上旋转。
但这种影响将主要由短期的抵消延迟所主导。
3）“打开”也是一个偏移打开，因此具有一定的长度，并且同样适用于上面的＃1点。
4）“开放”不是一个完美的开放，因为它具有边缘电容，这是重要的。
并且与频率是非线性的。
所以基本上这种行为是可以预期的。
标准的偏移延迟是匹配的（但通常不是相同的值），因此相位差保持接近180度。
对于您所做的单端口校准，VNA需要3个标准。
显然，如果开路和短路的相位相同的频率，你已经有效地删除了其中一个标准，因此只有两个标准。
所以VNA无法校准。
如果开路和短路之间的相位差太小，则误差校正仍然可以工作，但不太准确。
因此，180度是最佳值，标准设计尽可能接近。
但是相位差在所有频率下都不会精确到180度。
我不能把我的85050B连接到我的VNA看到，但如果有一个APC7套件，如85050B或85050D，短路和开路的零偏移延迟，我希望看到更小的变化
在N和3.5 mm等连接器上频率超过1的相位。
几种安捷伦应用笔记以及Joel的书中都包含了这类内容。
http://www.amazon.co.uk/Handbook-Microwave-Component-Measurements-Techniques/dp/1119979552我认为人们期望在史密斯圆图上看到一个简短或开放的点是很常见的，所以你不是
第一个，我怀疑你是最后一个质疑这个！
DaveEdited：drkirkby于2013年10月20日上午8:43



     以下为原文

  > {quote:title=Jiyuan wrote:}{quote}
> After SOLT calibration, I connect the short load to one port. The impedance point is not on the short circuit point of the S11 Smith Chart, but rotates by some degrees. So does the open load. But their phase difference is 180 deg. Why?

You don't say what VNA or cal kit you used, which is generally useful to do, but in this case it does not matter too much. 

There are several things here. 

1) The "short" is really an "offset short". It is a bit of transmission line, of impedance Zo usually 50 Ohms, of some length - typically a few mm, but expressed by HP/Agilent as a delay in ps. (Rohde and Schwarz in contrast express their delays in mm). Such an offset short can not be expected to behave like an ideal short.

2) The short has some inductance. It is usually negligible, but again that would make the point rotate on a Smith Chart. But such an effect will be much dominated by the offset delay of the short. 

3) The "open" is again an offset open, so has some length, and the same applies as in point #1 above. 

4) The "open" is not a perfect open, as it has fringing capacitance, which is significant. and is non-linear with frequency. 

So basically this behavior is to be expected. The offset delays of the standards are matched (but not normally the same value) so the phase difference stays close to 180 degrees. 

For the one-port calibration you did, the VNA needs 3 standards. Obviously if there was a frequency where the phase of the open and short were the same, you have effectively removed one of the standards, and so only have two. So the VNA could not calibrate. If the phase difference between the open and short are too small, the error correction can still work, but is less accurate. So with 180 degrees being the optimal value, the standards are designed as close to that as possible. But the phase difference wont be exactly 180 degrees at all frequencies. 

I can't be bothered to connect my 85050B to my VNA to see, but if one had an APC7 kit such as the 85050B or 85050D, where there is zero offset delay on the short and open, I would expect to see much smaller variation of phase with frequency than one sees on connectors such as N and 3.5 mm. 

This sort of thing is covered in several Agilent application notes, as well as Joel's book. 

http://www.amazon.co.uk/Handbook-Microwave-Component-Measurements-Techniques/dp/1119979552

I think people expecting to see a dot on a Smith Chart for a short or open is quite common, so you are not the first one, and I doubt you will be the last to question this! 

Dave

Edited by: drkirkby on Oct 20, 2013 8:43 AM

非常感谢，戴夫。
我们使用85054D校准套件（N型，50欧姆）。
据我所知，如果校准正确完成，史密斯圆图上的短点和开放点是“真实的”短而开放的。
由于偏移，短路或开路负载的相位被旋转。
VNA考虑所有效果以使校准正确。
实际上，我们需要“真正的”短点来找到1.3 GHz超导腔的失谐短平面。
济源



     以下为原文

  Thanks a lot, Dave. We use the 85054D cal kit (type-N, 50 ohm). As I understand from your post, if the calibration is done correctly, the short point and the open point on the Smith Chart are "real" short and open. The phase of the short or open load is rotated because of the offset. The VNA considers all the effects to make the calibration right. Actually, we need the "real" short point to find the detuned short plane of a 1.3 GHz superconducting cavity.

Jiyuan

> {quote：title = Jiyuan写道：} {quote}>非常感谢，戴夫。
我们使用85054D校准套件（N型，50欧姆）。
据我所知，如果校准正确完成，史密斯圆图上的短点和开放点是“真实的”短而开放的。
由于偏移，短路或开路负载的相位被旋转。
VNA考虑所有效果以使校准正确。
实际上，我们需要“真正的”短点来找到1.3 GHz超导腔的失谐短平面。
>>济源济源，我不是真的跟着你。
一旦你校准了VNA，如果你在史密斯圆图上放一个标记，比如5 GHz，它会告诉你在连接器参考平面上测量的阻抗*。
对于我所知道的任何连接器，它被定义为外导体的配合平面。
对于N来说肯定是正确的，尽管它可能不适用于其他类型。
外导体配合平面和短导线之间将存在一些物理距离。
我不知道你所拥有的标准的设计，因为我从未见过85054D。
所以我不能告诉你物理长度，虽然我不清楚即使你有它也会使用这些信息。
通过查看校准套件定义中给出的偏移延迟，您可以找到短路的电气延迟。
对于不同的校准套件，这些是不同的，对于N，它们对于N中的男性和女性是不同的。如果你去http://na.tm.agilent.com/pna/caldefs/stddefs.html挑选
您的校准套件和VNA型号应该为您提供参数，包括偏移延迟。
从那里，使用85054B校准套件查看PNA的值http://na.tm.agilent.com/pna/caldefs/PNA/85054D.htm人类可读的HTML页面显示男性短片的延迟为6.31
E-11s和女性短裤是2.80E-11秒。
安捷伦的某个人告诉我，用于生成HTML的代码会对数字进行舍入，因此它们可能不太准确，而数据文件（人类不可读）将是准确的。
用于85054D套件的HP 8720D VNA固件中的值为女性短路* 28.003 ps *男性短路时为63.106 ps。
它们可能不是最佳值，因为我的VNA无法校正短路的电感，并且HP可能会稍微调整偏移延迟值以补偿短路电感。
安捷伦的某个人能够给出确切的数字，但我怀疑是28.003 ps和63.106 ps是正确的。
因此它们是电延迟，但由于短路可能包含电介质，因此无法计算物理长度。
（您可能会根据PTFE的介电常数估算它们，大约为2.1，但我不明白为什么这对您有用）如果在VNA上应用等于偏移延迟的端口扩展（即28.003 ps或63.106）
ps），然后你会看到外导体参考平面的阻抗。
这将接近你最初预期的点，但正如我之前所写，短路电感和开路电容意味着它仍然不是一个完美的地方。
我想如果你更多地描述你的应用，以及你打算如何将N连接器连接到你的超导腔，有人可能能够帮助你更多。
戴夫



     以下为原文

  > {quote:title=Jiyuan wrote:}{quote}
> Thanks a lot, Dave. We use the 85054D cal kit (type-N, 50 ohm). As I understand from your post, if the calibration is done correctly, the short point and the open point on the Smith Chart are "real" short and open. The phase of the short or open load is rotated because of the offset. The VNA considers all the effects to make the calibration right. Actually, we need the "real" short point to find the detuned short plane of a 1.3 GHz superconducting cavity.
> 
> Jiyuan

Jiyuan,

I'm not really following you. 

Once you calibrate the VNA, if you put a marker on the Smith chart, say at 5 GHz, it will tell you the impedance measured *at the reference plane of the connector*. For any connector I know, that is defined as the mating plane of the outer conductors. It is certainly true for N, though it might not be for some other types. 

There will be some physical distance between the outer conductor mating plane and where the short is. I don't know the design of the standards you have, since I've never seen an 85054D. So I can't tell you the physical length, although it is not clear to me what use that information would be even if you had it. 

You can find the electrical delay to the short by looking at the offset delay given in the calibration kit definitions. These are different for different calibration kits, and in the case of N, they are different for the male and female in N. 

If you go to http://na.tm.agilent.com/pna/caldefs/stddefs.html pick your calibration kit and VNA model it should give you the parameters, including the offset delay. From there, looking at values for a PNA with the 85054B calibration kit

http://na.tm.agilent.com/pna/caldefs/PNA/85054D.htm

The human-readable HTML page says the delay on the male short is 6.31E-11s and on the female short is 2.80E-11 s. Someone from Agilent told me the code used to generate that HTML rounds the numbers, so they might not be too accurate, whereas the data files, which are no human readable, will be accurate. 

The values in the firmware of my HP 8720D VNA for the 85054D kit are

* 28.003 ps for the female short
* 63.106 ps for the male short. 

They might not be the best values, as my VNA can't correct for the inductance of the short, and it is possible HP tweaked the offset delay values a bit to compensate for the shorts inductance. Someone from Agilent would be able to give you the exact figures, but I suspect 28.003 ps and 63.106 ps are right. 

So they are the electrical delays, but since the short probably contains a dielectric, the physical lengths can't be calculated. (You might estimate them based on the permittivity of PTFE which is around 2.1, but I can't see why this is any use to you)

If you apply a port extension on the VNA equal to the offset delay (i.e. 28.003 ps or 63.106 ps), then you will see the impedance at the outer conductor reference plane. That will be close to the dots you initially expected, but as I wrote earlier, the shorts inductance and opens capacitance means it still wont be a perfect spot. 

I think if you describe your application a bit more, and how you intend connecting the N connector to your superconducting cavity, someone might be able to help you more. 

Dave

谢谢！
戴夫。
济源



     以下为原文

  Thanks! Dave.

Jiyuan

对Dave的评论只是一些补充评论。
如果在完成短路或开路（无相位旋转）的情况下测量偏移短路或偏移开路并进行误差校正，那么校准和测量就会出现问题。
因此必须将长度转换为包括速度因子的传播相位常数，因此在长度上更期望指定电延迟中的偏移。
然后，必须在某处定义或假设速度因子。
电延迟已经包括速度因子，它还用于计算传播损耗常数。
肯



     以下为原文

  Just some additional comments to Dave's comments.

If an offset short or offset open measured like a perfect short or open (no phase rotation) with error correction on, then there is something wrong with the calibration and measurement.

Specifying offsets in electrical delay is more desirable then in length since length must be converted to the propagation phase constant that includes a velocity factor.  Then, the velocity factor must be defined or assumed somewhere. The electrical delay already includes the velocity factor and it is also used to compute the propagation loss constant.

Ken