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电子发烧友william hill官网
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我们购买了两个评估套件：ZC706和ARDV9371，将它们连接在一起。
现在我们要修改从ADI获得的FPGA代码。 我已经安装了ZC706的许可证，后来又安装了JESD204的评估许可证（见附件）。 现在，当我尝试编译时，只有比特流生成失败： [Common 17-69]命令失败：此设计包含一个或多个不允许生成比特流的单元：i_system_wrapper / system_i / axi_ad9371_tx_jesd / inst / i_system_axi_ad9371_tx_jesd_0（jesd204_v7_0_1_topparameterized1） i_system_wrapper / system_i / axi_ad9371_rx_os_jesd / inst / i_system_axi_ad9371_rx_os_jesd_0（jesd204_v7_0_1_topparameterized0） i_system_wrapper / system_i / axi_ad9371_rx_jesd / inst / i_system_axi_ad9371_rx_jesd_0（jesd204_v7_0_1_top） 如果添加了新的IP核许可证，为了获取新许可证，需要通过在比特流生成之前重置和重新生成IP输出产品来更新当前网表。 我已经四处搜索，并尝试了https://www.xilinx.com/support/answers/58758.html中提出的解决方案，但“重置输出产品”根本无法使用。 我尝试过Vivado 2017.2和2016.2（后者可能更适合该项目）。 我无法以任何方式重新生成IP。 谢谢 以上来自于谷歌翻译 以下为原文 We have bought two evaluation kits: ZC706, and ARDV9371, to connect them together. Now we want to modify the FPGA code obtained from ADI. I have installed the licence for the ZC706, and later on the evaluation licence for the JESD204 (see attached). Now when I try to compile, only the bitstream generation fails with: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: i_system_wrapper/system_i/axi_ad9371_tx_jesd/inst/i_system_axi_ad9371_tx_jesd_0 (jesd204_v7_0_1_topparameterized1) i_system_wrapper/system_i/axi_ad9371_rx_os_jesd/inst/i_system_axi_ad9371_rx_os_jesd_0 (jesd204_v7_0_1_topparameterized0) i_system_wrapper/system_i/axi_ad9371_rx_jesd/inst/i_system_axi_ad9371_rx_jesd_0 (jesd204_v7_0_1_top) If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. I have searched around, and tried the solution proposed in https://www.xilinx.com/support/answers/58758.html, but "Reset Output Products" is simply not available to me. I have tried with Vivado 2017.2 and 2016.2 (the later is possibly better suited for the project). I am not able to regenerate the IP in any way. Thank you 
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16个回答
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Hitcachat@metraware.com
如果右键单击层次结构或IP源窗口中的IP XCI文件，您将看到“重置输出产品”选项。 如果你找不到它，你能告诉我们这个菜单的截图吗？ 谢谢，迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星） 以上来自于谷歌翻译 以下为原文 Hi tcachat@metraware.com If you right click on the IP XCI file in hierarchy or IP sources window, you will see the "reset output products" option. Can you show us a screenshot of this menu if you dont find it? Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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Hitcachat@metraware.com
>>我已经四处寻找，并尝试了解决方案：http：//www.xilinx.com/support/answers/58758.html，但“重置输出产品”根本无法使用。 当你说复位输出产品不适合你时，你的意思是什么？ 您只需在设计层次结构源窗口中单击JESD IP，右键单击并重置输出产品，然后生成输出产品。 如果它没有帮助，那么尝试从头开始创建项目，让我们知道结果。 问候 罗希特 -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用，请回答“接受为解决方案”。 将Kudos发送给您认为有用且回复的帖子.------------------------------------ -------------------------------------------------- -------- RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi tcachat@metraware.com >>I have searched around, and tried the solution proposed in https://www.xilinx.com/support/answers/58758.html, but "Reset Output Products" is simply not available to me. What do you mean when you say reset output products is not available for you? You need to simply click on JESD IP in the design hierarchy source window, right click and do reset output products followed by generate output products. Still if it didn't help then try creating the project from scratch and let us know the results. Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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谢谢。
附件是一个屏幕截图。 “重置输出产品......”根本不可用（屏蔽？）。 它与Vivado 2017.2类似，只是IP被锁定（红锁）。 以上来自于谷歌翻译 以下为原文 Thank you. Attached is a screen shot. The "Reset Output Products..." is simply not available (shielded ?). It is similar with Vivado 2017.2, except that the IP is locked (red lock). |
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我可以正确看到复位输出。
你能检查你的许可证状态吗？ 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。 以上来自于谷歌翻译 以下为原文 I can see reset output correctly . Can you check your license status Thanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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Hitcachat@metraware.com
从屏幕截图看，您的块设计（BD）中添加了多个IP。 如果是这种情况，您可以在设计层次结构源窗口下转到BD，右键单击并重置输出产品，然后生成输出产品吗？ 现在运行综合，实现和比特流。 问候 罗希特 -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用，请回答“接受为解决方案”。 将Kudos发送给您认为有用且回复的帖子.------------------------------------ -------------------------------------------------- -------- RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi tcachat@metraware.com From the screen shot it looks like you have multiple IPs which has been added in your Block design(BD). If that is the case, can you go to BD under design hierarchy source window, right click and do reset output products followed by generate output products? Now run the synthesis, implementation and bitstream. Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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tcachat@metraware.com，
对于块设计，您将无法看到单个IP的复位输出产品。 您需要选择（右键单击）bd文件，如下所示，然后选择重置输出产品，然后生成输出产品： --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 tcachat@metraware.com, For block design you will not be able to see the reset output products for single IP. You need to select (right click) the bd file as shown below and select reset output products followed by generate output products: --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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谢谢你的帮助......不幸的是，这还不够。
下面的第一张图片是Balkrishan，Rohit和Syed的第二张图片...... 我也尝试打开system.bd但它没有帮助。 以上来自于谷歌翻译 以下为原文 Thank you for your help... Unfortunately it is not sufficient. The first picture below is for Balkrishan, the second one for Rohit and Syed... I also tried to open system.bd but it did not help. |
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首先，您需要升级BD IP。
您可以使用vivado版本共享项目。 我们可以帮到你 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。 以上来自于谷歌翻译 以下为原文 First you need to upgarde the BD IPs . You can share the project with vivado version . We can do it for youThanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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tcachat@metraware.com，
从Vivado，单击工具 - >报告 - >报告IP状态以升级您的设计。 您还可以运行以下TCL命令： report_ip_status -name ip_status --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 tcachat@metraware.com, From Vivado, click on Tools-->Report-->Report IP status to upgrade your design. You can also run the following TCL command: report_ip_status -name ip_status --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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事实上，我发现某处我必须升级IP，但我没有设法做到这一点，显然Vivado 2016.2并不需要。
下面有两个截图：一个用于Vivado 2016.2，另一个用于Vivado 2017.2。 我试着在一分钟内上传我的项目 以上来自于谷歌翻译 以下为原文 Indeed I found somewhere that I have to upgrade the IP, but I did not manage to do it, and apparently is was not needed for Vivado 2016.2. There are two screenshots below: one for Vivado 2016.2, the other for Vivado 2017.2. I try to upload my project in a minute |
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我已将我的项目发送到Balkrishan，我无法在此处上传。
顺便说一句，我刚进入JESD204休息室，我找到了 https://www.xilinx.com/products/intellectual-property/ef-di-jesd204/ef-di-jesd204-software-requirements.html 需要Vivado®2017.3，我没有安装。 但该项目来自 https://github.com/analogdevicesinc/hdl/tree/adrv9371-init-lw/projects/adrv9371x/zc706 应该用Vivado 2016.2编译？ 以上来自于谷歌翻译 以下为原文 I have sent my project to Balkrishan, I was not able to upload it here. By the way, I just got access to the JESD204 Lounge, and I found on https://www.xilinx.com/products/intellectual-property/ef-di-jesd204/ef-di-jesd204-software-requirements.html That Vivado® 2017.3 is needed, which I did not install. But the project from https://github.com/analogdevicesinc/hdl/tree/adrv9371-init-lw/projects/adrv9371x/zc706 should compile with Vivado 2016.2? |
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tcachat@metraware.com
它要求在2017年升级IP，因为原始设计是在2016年制作的。 但您也可以在2016.2中使用新许可证。 如果您遇到问题，请告诉我们。 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 tcachat@metraware.com It asks to upgrade the IP in 2017.2 as the original design was made in 2016.2. But you can use the new license in 2016.2 as well. Let us know if you run into issues. Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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我花了很多时间在不同的william hill官网
上搜索，并尝试使用我的电脑。
目前我的Linux虚拟机有点好，因为它的Vivado似乎认可了ZC706的许可证（与https://forums.xilinx.com/t5/Installation-and-Licensing/vivado-don-t-find相同的问题） -My主机-ID / TD-p / 663265）。 所以我试着在VM上编译项目。 它走得更远，但由于各种原因它没有完成。 附件是最后一个日志。 然后我将这个项目复制到我的Windows机器（在同一台计算机上），我第一次可以访问“重置输出产品......”和“生成输出产品...”但是生成失败了，请参见随附的屏幕截图 。 谢谢 PS。 屏幕截图来自Vivado 2016.2，Vivado 2017.2我仍然无法访问“重置输出产品......”和“生成输出产品......”。 vivado.log 1331 KB 以上来自于谷歌翻译 以下为原文 I have spent many hours searching in different forums, and trying on my computer. For now my Linux Virtual Machine is a bit better, because its Vivado seems to recognize the Licence for ZC706 (same problem as https://forums.xilinx.com/t5/Installation-and-Licensing/vivado-don-t-find-my-host-ID/td-p/663265). So I tried to compile the project on the VM. It went a bit further, but for various reason it did not complete. Attached is the last log. Then I copied this project to my windows machine (on the very same computer), and I could access to "Reset Output Products…" and "Generate Output Products…" for the first time... But generation failed, see attached screen shot. Thank you PS. The screen shot is from Vivado 2016.2, with Vivado 2017.2 I still do not have access to "Reset Output Products…" and "Generate Output Products…". |
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在我解决了一些问题之后，我仍然无法编译。
我认为最后一个问题是我的虚拟机没有足够的RAM（“父进程（pid 3071）已经死了。这个助手进程现在将退出”）。 我把它限制在3.5 Go，因为前一段时间它足以用于XC7Z020（ZedBoard）。 现在我尝试使用7 Go，关闭我PC上的所有其他应用程序，这个过程可能会更进一步（大约48分钟）。 附件是最后一个日志。 vivado.log 1786 KB 以上来自于谷歌翻译 以下为原文 After I have solved some of the issues, I still cannot compile. I think one of the last problem was that my virtual machine did not have enough RAM ("Parent process (pid 3071) has died. This helper process will now exit"). I limited it to 3.5 Go, because some time ago it was sufficient for the XC7Z020 (ZedBoard). Now I have tried with 7 Go, closed every other application on my PC, and the process could go a bit further (for about 48 min). Attached is the last log. |
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我已经从“新”项目重新启动，因为它是从Github下载的，并为虚拟机提供了更多的RAM（现在为5.2 GB，为Windows保留一些）。
看来我可以走得更远，因为它现在正在编制数小时。 没有错误，但没有结果。 你知道它需要多长时间吗？ 以上来自于谷歌翻译 以下为原文 I have restarted from the "fresh" project, as it was downloaded from Github, and given some more RAM to the Virtual Machine (for now 5.2 GB, to keep some for Windows). It seems I could go a bit further, in the sense that it is compiling for hours now. Without error, but without result. Do you have an idea how long it could take? |
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在等待了几个小时（编译正在进行中的白天和黑夜）之后，我已经使用更多内存升级了我的PC，并以8 GB重新启动了我的虚拟机。
编译在大约40分钟内完成。 现在我可以开始工作了（我还有其他一些问题，但这是另一个故事）。 我曾经在ZedBoard上经历过，当它缺乏资源时，编译只是中止，或者我可以看到交换过程。 使用ZC706和我的配置，我不知道它可以花多长时间，以及它是否会成功。 谢谢 以上来自于谷歌翻译 以下为原文 After waiting for hours (compilation was in progress night and day), I have upgraded my PC with some more RAM, and restarted my virtual machine with 8 GB. Compilation was finished in about 40 minutes. Now I can start to work (I have some other issues, but it is another story). I had experienced in the past with a ZedBoard that the compilation simply abort when it lacks resources, or that I can see the swap process. With the ZC706 and my configuration I had no idea how long it could take, and whether it would succeed. Thank you |
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