您是在尝试学习FPGA（硬件）设计，还是在尝试学习Verilog语言？
不管。
使用Verilog推断从NAND门构建的锁存器和寄存器是不明智的，并且误用了该语言。
选择一个不同的教科书。
只需浏览XST语言模板，您就可以了解更多信息，更好地学习，更好地学习。
运行ISE Navigator，单击灯泡图标，浏览许多编码示例。
这是在Verilog中推断出简单的边沿触发D触发器的方法：
reg reg_Q = 0;
//一个单比特寄存器，初始状态为'0'
总是@（posedge reg_CLOCK）reg_Q
这就是在Verilog中推断出一个简单的3位二进制计数器的方法：
reg [2：0] counter = 0;
//一个3位计数器，初始状态为'0'
总是@（posedge reg_CLOCK）柜台
你越早离开门级设计（除非绝对必要），你越早设计系统而不是计数器。
来自新用户william hill官网
README线程：
设计技巧：
我是FPGA设计的初学者 - 我从哪里开始？
在线培训教程等：链接＃1链接＃2线程＃1线程＃2线程＃3
VHDL / Verilog教程和书籍建议线程＃1链接＃1线程＃2线程＃3
FPGA设计书推荐线程＃1
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索william hill官网
（并搜索网页）以寻找类似的主题。
不要在多个william hill官网
上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付william hill官网
帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
Are you trying to learn FPGA (hardware) design, or are you trying to learn the Verilog language?
No matter. Using Verilog to infer latches and registers built from NAND gates is unwise and a mis-use of the language.
Choose a different textbook.
You can learn
more, learn
better, and learn
more correctly merely by browsing through the
XST Language Templates.
Run the
ISE Navigator, click on the light-bulb icon, and browse through the many
many coding examples.
This is how a simple edge-triggered D-flipflop is inferred in Verilog:
reg reg_Q = 0; // a single-bit register, initial state is '0'
always @(posedge reg_CLOCK) reg_Q <= reg_DIN;
And this is how a simple 3-bit binary counter is inferred in Verilog:
reg [2:0] counter = 0; // a 3-bit counter, initial state is '0'
always @(posedge reg_CLOCK) counter <= counter + 1;
The sooner you leave gate-level design behind (except where absolutely necessary), the sooner you will be designing
systems rather than
counters.
From the New Users Forum README thread:
Design skills:
I'm a beginner with FPGA designs - where do I start? Online training tutorials and more: link#1 link#2 thread#1 thread#2 thread#3
VHDL/Verilog tutorials and book recommendations thread#1 link#1 thread#2 thread#3
FPGA design book recommendations thread#1
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
您是在尝试学习FPGA（硬件）设计，还是在尝试学习Verilog语言？
不管。
使用Verilog推断从NAND门构建的锁存器和寄存器是不明智的，并且误用了该语言。
选择一个不同的教科书。
只需浏览XST语言模板，您就可以了解更多信息，更好地学习，更好地学习。
运行ISE Navigator，单击灯泡图标，浏览许多编码示例。
这是在Verilog中推断出简单的边沿触发D触发器的方法：
reg reg_Q = 0;
//一个单比特寄存器，初始状态为'0'
总是@（posedge reg_CLOCK）reg_Q
这就是在Verilog中推断出一个简单的3位二进制计数器的方法：
reg [2：0] counter = 0;
//一个3位计数器，初始状态为'0'
总是@（posedge reg_CLOCK）柜台
你越早离开门级设计（除非绝对必要），你越早设计系统而不是计数器。
来自新用户william hill官网
README线程：
设计技巧：
我是FPGA设计的初学者 - 我从哪里开始？
在线培训教程等：链接＃1链接＃2线程＃1线程＃2线程＃3
VHDL / Verilog教程和书籍建议线程＃1链接＃1线程＃2线程＃3
FPGA设计书推荐线程＃1
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索william hill官网
（并搜索网页）以寻找类似的主题。
不要在多个william hill官网
上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付william hill官网
帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
Are you trying to learn FPGA (hardware) design, or are you trying to learn the Verilog language?
No matter. Using Verilog to infer latches and registers built from NAND gates is unwise and a mis-use of the language.
Choose a different textbook.
You can learn
more, learn
better, and learn
more correctly merely by browsing through the
XST Language Templates.
Run the
ISE Navigator, click on the light-bulb icon, and browse through the many
many coding examples.
This is how a simple edge-triggered D-flipflop is inferred in Verilog:
reg reg_Q = 0; // a single-bit register, initial state is '0'
always @(posedge reg_CLOCK) reg_Q <= reg_DIN;
And this is how a simple 3-bit binary counter is inferred in Verilog:
reg [2:0] counter = 0; // a 3-bit counter, initial state is '0'
always @(posedge reg_CLOCK) counter <= counter + 1;
The sooner you leave gate-level design behind (except where absolutely necessary), the sooner you will be designing
systems rather than
counters.
From the New Users Forum README thread:
Design skills:
I'm a beginner with FPGA designs - where do I start? Online training tutorials and more: link#1 link#2 thread#1 thread#2 thread#3
VHDL/Verilog tutorials and book recommendations thread#1 link#1 thread#2 thread#3
FPGA design book recommendations thread#1
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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