对于XIlinx，4 GB RAM还是更少

您定位的设备是什么？
你知道你的设备利用率是多少吗？
200个或更多模块听起来像它可能包含很多逻辑。
如果您的设计非常繁忙，即使资源过多，这也可能是您缺乏内存问题的根源。
问候，
霍华德
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

What device are you targeting? Do you know what your device utilisation is? 200 or more modules sounds like it could contain A LOT of logic. If you have an extremely busy design, even over-resourced, this could be the source of your lack of memory problem.
 
Regards,
 
Howard
 
----------
"That which we must learn to do, we learn by doing." - Aristotle

我正在使用顶点4，但现在我只使用Isim来查看模拟结果。
我的输入是（a＆amp; b）194位二进制值，并且在通过在特征的有限域中使用不可约多项式y ^ 2 = x ^ 97 + X ^ 12 + 2进行减少后输出也是194位。是的我的计算
我认为......我的总模块现在已经停止了
1：3 ^ 97加法器（加法器194位输入a＆amp; b和输出194）
2：3 ^ 97减法器（减法器194位输入a＆amp; b和输出194）
3：3 ^ 97 karat suba乘数（乘法器194位输入a＆amp; b和输出386）
4：在一个时钟内从386位减少到194位
5：通过将给定值194位的乘法3 ^ 97-2乘以双倍并且添加相当广泛的算法来找到194位输入值的倒数。
6：最后一个模块是使用所有以前的模块来计算椭圆曲线上的点加法，它没有给出任何值，xilinx进入无响应状态
注意：
通过使用不可约多项式将每个乘法结果减少到194位，并且3 ^ 97-2是154位值



以下为原文

SIr i am using vertex 4 but now i am using only Isim to see only the simulation results. my inputs are(a &b) 194 bit binary values and out put is also 194 bits after reducing by using the irreducible polynomial y^2=x^97+X^12+2 in finite fields of characterstics 3. yes my computation is very expansive i think...my total modules uptill now are 
1:  3^97 adder(adder 194 bits inputs a&b and out 194)
2:  3^97 subtractor(subtractor 194 bits inputs a&b and out 194)
3:3^97  karat suba multiplier(multiplier 194 bits inputs a&b and out 386)
4: reduction from 386 bits to 194 bits which i s done in one clock
5: find inverse of 194 bit input value by taking power 3^97-2 multiplications of the given value 194 bits by double and add algorithms which is quite expansive.
6: and the last module is to use all the previous modules to calculate the point addition on the elliptic curves which did not give any value and xilinx go in not responding state 
Note:
after every multiplication result is reduced to 194 bits by using irreducible polynomial and 3^97-2 is 154 bit value

您是否在ISim窗口中看到任何消息，表明在开始模拟时它正在努力编译？
您的设计是否包含可能导致模拟器挣扎的组合反馈计时迭代（for循环）（因为它不处理绝对设备延迟，而是delta延迟）？
如果您将设计扩展为使用更小的数据/模块子集，会发生什么？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Do you see any messages in the ISim window that indicate it is struggling with the compilation when you begin the simulation?
 
Does your design include combinatorial feedback or non-clocked iterations (for loops) that may cause the simulator to struggle (as it does not deal with absolute device delay, rather delta delays)?
 
What happens if you scale your design back to use a much smaller subset of data/modules?
----------
"That which we must learn to do, we learn by doing." - Aristotle

我收到错误消息，指出内存不足或冲突内存不足.....用一些文件（ini。）文件增加物理内存
2：是的，它包括组合块和顺序块
3：当我运行一个小模块时，它可以非常有效地计算输出。
通过添加更多模块有效降低
请告诉我，xilinx中的子模块是否存在单独的IO资源限制。



以下为原文

I got the error message that there is run short of memory or conflict memory.....increase your physical memry by some file (ini.) file
2: yes it includes both combinational and sequential blocks
3:when i run a small module it computes the out put very efficiently. efficiently decreases with the addition of more modules
Please tell me that are there seperate IO resource limitation in xilinx for submodules. 

如果在完整模拟运行时使用任务管理器（或其他类似类型），您可以在模拟过程中观察内存使用情况吗？
这些天4GB对我来说听起来不那么重要。
您没有提到您正在使用的操作系统，但这可能会耗尽您的可用内存。
您是否可以访问具有更多内存的另一台计算机？
也许你可以附上你的代码（或它的一个例子）来展示你的编码风格。
它可能是一种更有效的编码风格，您将能够完成您的模拟。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

If you use Task Manager (or some other similar type) when the full simulation runs can you observe your memory usage as the simulation progresses? 4GB doesn't sound so much to me these days. You didn't mention which OS you are using but this could be using up quite a bit of your available memory.
 
Do you have access to another machine with more memory?
 
Maybe you could attach your code (or an example of it) that demonstrates your coding style. It may be with a more efficient coding style you will be able to complete your simulations.
----------
"That which we must learn to do, we learn by doing." - Aristotle

先生，我发送的是verilog文件，即（.V）文件代码。
主要模块是inverse_3_97.SIr运行它并告诉我在多天里我遇到的错误在哪里。
将输出结果输出到此代码。
当我扩展此代码时，xilinx没有响应。
当我扩展逆模块被多次调用....谢谢
反码 -  Copy.zip 19 KB



以下为原文

Sir i am sending you the  verilog files i.e (.V) file code. the main module is inverse_3_97.SIr plz run it and tell me where is the error which i have stuck for many days. uptill this code the output comes. when i extend this code xilinx goes to not responding. when i extend  inverse module is called multiple times....Thanks
            inverse code - Copy.zip ‏19 KB

尝试升级你的RAM。
它可能需要升级。



以下为原文

Try to upgrade your RAM. It might need an upgrade for that.

非常感谢先生.....我的编程风格很差或者这个项目使用的资源非常多......再次提出你的建议......这很有帮助。



以下为原文

Thanks a lot sir.....is my programming style is poor or the resources  used by this project is very much... again thnks for your suggestions... it helpsme a lot.

您可以尝试运行设计的综合，看看合成器（我假设XST）是什么造成的。
如果你得到很多，例如，闩锁警告或组合循环警告，那么你就会知道你的编码在哪里挣扎。
我不是Verilog的专家，我没有完成你的项目，但有可能得到帮助你的工具。
有关于各种设备系列和XST的编码风格的指南文档，因此我建议您阅读它们并将您的代码与提供的示例进行比较。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

You could try running a synthesis of the design and see what the synthesiser (I assume XST) makes of it. If you get a lot of, for example, latch warnings or combinatorial loop warnings then you'll have an idea of where your coding is struggling.
 
I'm no expert in Verilog and I haven't been through your project but it is possible to get the tools to help you. There are guide documents on coding style for the various device families and for XST, so I suggest you read them and compare your code to the provided examples.
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"That which we must learn to do, we learn by doing." - Aristotle