有没有人推荐使用Vivado的好处理器？

HI，
我认为对于8GB RAM机器来说，25分钟是常见的，如果你需要它更快，试试16GB
另请参阅下面UG的“系统内存建议”部分以及各种设备的链接。
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug973-vivado-release-notes-install-license.pdf
http://www.xilinx.com/design-tools/vivado/memory.htm
希望这可以帮助
问候，
Vanitha
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以下为原文

HI,
 
I think 25min is common for 8GB RAM machines, if you need it more faster try with 16GB
Also please refer "System Memory Recommendations" section of below UG and links for various devices.
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug973-vivado-release-notes-install-license.pdf
 
http://www.xilinx.com/design-tools/vivado/memory.htm
 
 
Hope this helps
 
Regards,
Vanitha
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你能检查一下是否启用了多处理？
根据UG904（Vivado Design Suite用户指南实施）：
“还有一个适用于所有任务的通用限制，基于操作系统。对于Windowssystems，限制为2;对于Linux系统，限制为8.可以使用名为general.maxThreads的参数更改限制。更改
limit：Vivado％set_param general.maxThreads -where新限制必须是1到8之间的整数。示例：在Windowssystem上：Vivado％get_param general.maxThreads2这意味着无论处理器数量多少，所有任务都限制为2个线程或
任务执行。如果系统至少有8个处理器，你可以将限制设置为8并允许每个任务使用最大线程数.Vivado％set_param general.maxThreads 8“



以下为原文

Can you check if multi processing is enabled?
 
According to UG904 (Vivado Design Suite User Guide Implementation):
 
 
"There is also a general limit that applies to all tasks and is based on the OS. For Windows
systems, the limit is 2; for Linux systems the limit is 8. The limit can be changed using a
parameter called general.maxThreads. To change the limit:
Vivado% set_param general.maxThreads
—where the new limit must be an integer from 1 to 8, inclusive. Example: On a Windows
system:
Vivado% get_param general.maxThreads
2
This means all tasks are limited to 2 threads regardless of number of processors or the task
being executed. If the system has at least 8 processors, you can set the limit to 8 and allow
each task to use the maximum number of threads.
Vivado% set_param general.maxThreads 8"

它确实使用2个线程用于P＆amp; R但不用于合成。
这需要花费最多的时间



以下为原文

It does use 2 threads for P&R but not for synthesis. This is what takes the greatest amount of time

似乎即使我只在verilog文件中更改了一件事，整个设计也会再次合成。
有没有办法让它重做已更改的模块？
例如，如果我有一个AXI总线，MIG，一些IP 1和2.如果我改变IP 1，它真的需要重做其他的吗？



以下为原文

It seems that even if I only change one thing in a verilog file, the whole design gets synthesized again. Is there not a way for it to just redo the module that has changed? For instance if I have an AXI bus, MIG, some IP 1 and 2. If I change IP 1 does it really need to redo the others?