如何使用Xilinx工具进行自下而上的合成？

你好
检查以下链接
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf
问候，萨蒂什-----------------------------------------------
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以下为原文

Hi
 
Check the below link
 
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf
Regards,

Satish

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你好
检查以下链接
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
Check the below link
 
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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嗨，
要避免展平层次结构，还可以在“综合”选项中使用简单的开关。
-flatten_hierarchy应该是none。
有关详细信息，请参阅第9页-http：//www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
To avoid flattening hierarchy, you can also use a simple switch in the Synthesis options.
 
–flatten_hierarchy should be given as none.
 
Check more on this on Pg 9 - http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

谢谢您的回复。
在本手册中有一段简短地概念性地谈论自下而上的综合。
但是有没有关于这个主题的详细材料或教程？
（一些设计实例将非常有用。）



以下为原文

Thank you for your reply.
 
There is a paragraph talking about the Bottom-Up synthesis briefly and conceptually in this manual. But is there any detailed materials or tutorials on this topic? (Some design examples will be really helpful.)

jmgrn写道：
谢谢您的回复。
在本手册中有一段简短地概念性地谈论自下而上的综合。
但是有没有关于这个主题的详细材料或教程？
（一些设计实例将非常有用。）
我想有人应该问，“谁在乎呢？”
想一想。
综合工具将首先解析和分析（编译）每个单独的实体。
通常，这是自下而上完成的，因为合成器需要知道在较高层实体中实例化的每个较低层实体的端口列表。
如果您在代码中包含所有较低级实体的组件声明，然后实例化这些组件，则这不是必需的，因为组件声明告诉分析器“这是我们将如何与这些较低级别进行通信
事情，稍后处理细节。“
当然，在代码中包含这些组件声明意味着双重输入（一次用于声明，一次用于实例化），这使得错误变得容易。
（当低级实体的端口列表发生更改但您没有更改组件声明时会发生什么？）
一个常用的解决方法是将组件声明放在一个包中，但这要求在使用它的实体之前分析包。
现代习语是使用实体的直接实例化。
这完全取消了组件声明。
但这也要求首先将较低级别（实例化）实体分析到工作（或指定）库中。
这基本上是自下而上的综合。
值得注意的是，以自下而上的方式首先分析较低级别的要求并不是现代工具的问题。
XST，Vivado，Synplify和Mentor Precision将在将源添加到项目或修改时对所有源进行分析，然后它们将自动确定正确的编译顺序，因此您不必担心它。
（无论出于何种原因，一些仿真工具都不这样做; Aldec Active-HDL从旧版本8.3开始需要您将源文件放在正确的分析顺序中。）
所以这个饼干的关键在于你不必担心这一切，这一切都是自动发生的。
----------------------------是的，我这样做是为了谋生。



以下为原文

jmgrn wrote:
Thank you for your reply.
 
There is a paragraph talking about the Bottom-Up synthesis briefly and conceptually in this manual. But is there any detailed materials or tutorials on this topic? (Some design examples will be really helpful.)

I suppose one should ask, "Who cares?" Think about it.
 
The synthesis tools will start by parsing and analyzing (compiling) each individual entity. Generally, this is done bottom-up simply because the synthesizer needs to know the port list of each lower-level entity instantiated in a higher-up entity.
 
In the case where you include component declarations for all lower-level entities in your code and then you instantiate those components, this is not strictly necessary, because the component declarations tell the analyzer "here is how we'll talk to these lower-level things, deal with the details later." Of course, including these component declarations in your code means double typing (once for the declaration, once for the instantiation) and this makes errors easy. (What happens when the lower-level entity's port list has changed but you didn't change the component declaration?)
 
One commonly-used workaround to this is to put the component declarations in a package, but this requires that the package be analyzed before the entity which uses it. 
 
The modern idiom is to use direct instantiation of entities. This dispenses with the component declaration entirely. But this also requires that the lower-level (instantiated) entity be analyzed into the work (or specified) library first. This is basically bottom-up synthesis.
 
It's worth noting that the requirement that lower-level entites be analyzed first in this bottom-up manner isn't a problem with modern tools. XST, Vivado, Synplify and Mentor Precision will all analyze sources as they're added to a project or modified, and then they'll automatically determine the proper order of compilation so you don't have to worry about it. (Some simulation tools don't do that, for whatever reason; Aldec Active-HDL as of the old-ish 8.3 version requires you to put your source files in the correct analysis order.)
 
So the crux of this biscuit is that you don't have to worry about any of this, it all happens automatically.
----------------------------Yes, I do this for a living.

嗨mgrn
如果您有兴趣尝试，有一个关于分层设计的教程 -  http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug946-vivado-hierarchical-design-tutorial.pdf
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi mgrn
 
 
There is a tutorial on hierarchial design if you are interested to try - http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug946-vivado-hierarchical-design-tutorial.pdf 
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

>>我想有人应该问，“谁在乎？”
考虑一下。如果他们想要快速合成，任何拥有大型设计且重复实例化相同块的人都应该关心。
自下而上合成加速了这类设计的合成。
一次合成块，它们只使用了很多次。
在自顶向下合成中，特别是对于层次结构展平或重建选项，同一块会多次合成。
至少那是合成工具不是很聪明的想法。
这些天他们可能会自己注意到这一点。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

>> I suppose one should ask, "Who cares?" Think about it.

anyone who has a large design with repetitive instantiation of identical blocks should care if they want fast synthesis.
bottom up synthesis accelerates synthesis of this type of design. One synthesizes the block(s) once and they are just used many times. In top-down synthesis, especially with hierarchy flatten or rebuild options, the same block gets synthesized many times. At least that was the idea when synthesis tools were not very smart. These days they may notice this by themselves or not.- Please mark the Answer as "Accept as solution" if information provided is helpful.
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