怎么将GTX ECOMMON和GTX ECHANNEL连接为图像吗？

仅在共享逻辑模式下使用极光时，我得到了以下内容。
[放置30-140]无法安排的位置！
GTXE_COMMON / GTXE_CHANNEL时钟组件对未放置在可路由的站点对中。
如果GTXE_COMMON组件位于同一时钟区域，则GTXE_COMMON组件可以使用GTXE_COMMON和GTXE_CHANNEL之间的专用路径。
如果此子设计可接受此子优化条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为WARNING。
但是，强烈建议不要使用此覆盖。
这些示例可以直接在.xdc文件中使用，以覆盖此时钟规则。
system_i / aurora_8b10b_0 /安装/ gt_common_support / gtxe2_common_i（GTXE2_COMMON.QPLLOUTCLK）被临时放置由clockplacer上GTXE2_COMMON_X1Y1 system_i / aurora_8b10b_0 /安装/ system_aurora_8b10b_0_0_core_i / gt_wrapper_i / system_aurora_8b10b_0_0_multi_gt_i / gt0_system_aurora_8b10b_0_0_i / gtxe2_i（GTXE2_CHANNEL.QPLLCLK）被锁定到GTXE2_CHANNEL_X1Y0上述错误可能可能
与其他连接的实例相关。
以下是所有相关时钟规则及其各自实例的列表。
时钟规则：rule_bufds_gtxchannel_intelligent_pin状态：PASS规则说明：驱动GTXChannel的BUFDS必须放在相同或相邻的时钟区域（顶部/底部）system_i / aurora_8b10b_0 / inst / IBUFDS_GTE2_CLK1（IBUFDS_GTE2.O）被锁定到IBUFDS_GTE2_X1Y1 system_i / aurora_8b10b_0
/安装/ system_aurora_8b10b_0_0_core_i / gt_wrapper_i / system_aurora_8b10b_0_0_multi_gt_i / gt0_system_aurora_8b10b_0_0_i / gtxe2_i（GTXE2_CHANNEL.GTREFCLK0）被锁定到GTXE2_CHANNEL_X1Y0时钟规则：rule_bufds_gtxcommon_intelligent_pin状态：PASS规则说明：甲BUFDS驱动GTXCommon必须都放置在相同的或相邻的区域时钟（顶部/
底部）system_i / aurora_8b10b_0 /安装/ IBUFDS_GTE2_CLK1（IBUFDS_GTE2.O）被锁定到IBUFDS_GTE2_X1Y1 system_i / aurora_8b10b_0 /安装/ gt_common_support / gtxe2_common_i（GTXE2_COMMON.GTREFCLK0）被临时放置由GTXE2_COMMON_X1Y1时钟规则clockplacer：rule_gt_bufg状态：PASS规则说明：甲
GT驾驶BUFG必须放在同一半
该装置system_i / aurora_8b10b_0 /安装/ system_aurora_8b10b_0_0_core_i / gt_wrapper_i / system_aurora_8b10b_0_0_multi_gt_i / gt0_system_aurora_8b10b_0_0_i / gtxe2_i（GTXE2_CHANNEL.TXOUTCLK）的侧（顶部/底部）被锁定到GTXE2_CHANNEL_X1Y0和system_i / aurora_8b10b_0 /安装/ clock_module_i / user_clk_buf_i（BUFG.I）是暂时
由clockplacer放置在BUFGCTRL_X0Y3上
我们如何解决这个问题？



以下为原文

I got folowing while using aurora in shared logic mode alone.

• [Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets system_i/aurora_8b10b_0/inst/gt_common_support/gt_qpllclk_quad1_out] > system_i/aurora_8b10b_0/inst/gt_common_support/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X1Y1 system_i/aurora_8b10b_0/inst/system_aurora_8b10b_0_0_core_i/gt_wrapper_i/system_aurora_8b10b_0_0_multi_gt_i/gt0_system_aurora_8b10b_0_0_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X1Y0 The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_bufds_gtxchannel_intelligent_pin Status: PASS Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region (top/bottom) system_i/aurora_8b10b_0/inst/IBUFDS_GTE2_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y1 system_i/aurora_8b10b_0/inst/system_aurora_8b10b_0_0_core_i/gt_wrapper_i/system_aurora_8b10b_0_0_multi_gt_i/gt0_system_aurora_8b10b_0_0_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X1Y0 Clock Rule: rule_bufds_gtxcommon_intelligent_pin Status: PASS Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region (top/bottom) system_i/aurora_8b10b_0/inst/IBUFDS_GTE2_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y1 system_i/aurora_8b10b_0/inst/gt_common_support/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X1Y1 Clock Rule: rule_gt_bufg Status: PASS Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device system_i/aurora_8b10b_0/inst/system_aurora_8b10b_0_0_core_i/gt_wrapper_i/system_aurora_8b10b_0_0_multi_gt_i/gt0_system_aurora_8b10b_0_0_i/gtxe2_i (GTXE2_CHANNEL.TXOUTCLK) is locked to GTXE2_CHANNEL_X1Y0 and system_i/aurora_8b10b_0/inst/clock_module_i/user_clk_buf_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y3
  

HOW CAN WE RESOLVE THISS?

我知道驱动Aurora时钟的QPLL与Aurora的时钟区域不同。
请查看用于以太网和Aurora内核的两个收发器的位置，并确保它们位于相同的GT quad中。
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----------------------------别忘了回复，给予kudo并接受为解决方案---------
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以下为原文

I understand that the QPLL driving the clocks to Aurora is in a different clock region to that of Aurora.

Please review the location of both transceivers used for ethernet and Aurora cores and ensure they are in the same GT quad.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
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我附加了关于以太网位置的gtx的图像。
来到Aurora，我选择了X1Y0。
我猜，我选择了相同的四边形（GTQ0）。
问题出在哪里？



以下为原文

I am attaching image which tells about gtx for ethernet location.
Coming to Aurora ,I chose X1Y0.
I guess ,i have chosen same quad (GTQ0).
Where would be the problem?

如果可能，您可以共享一个测试用例来重现该问题吗？
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----------------------------别忘了回复，给予kudo并接受为解决方案---------
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以下为原文

If possible, can you share a test case to reproduce the issue?------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

Hi venkataI需要澄清我想使用一个四合一说117（GTXs-4）。我们正在使用Aurora协议。其他的，我们有单独的四块板，每个单独的GTX.Coming四个GTX板，我想通过4 gtxs传输数据
同一时间。（所有应该在上升点 - 起始点发送帧/单流字应该是相同的。）我们如何实现这一点？我们测试了很多情况。我们观察到有些时候它正在工作/有时它没有。
为什么呢？在四核中，One GTx是Master /共享逻辑其他3-GTX是slave / with out example design。在块设计中，我们将用户时钟从master映射到slave，qpll lock out和sync clock，pll signal as other as
在数据表中。我们如何同步来自所有四个GTX的用户时钟？我们需要在主板上同时发送数据字（我的要求）.Userclock是10ns。我们将Microblaze添加到块设计中，其中有四个auroras.my板卡
系统时钟我们10ns。有时你需要从Microblaze通过BRAM或GPIO获取数据。当我们尝试采用dat时
一个来自处理器系统，并映射到极光的tx_data，我们观察到，错过同步。上面的解决方案是什么？来微博系统，我们有时钟向导，锁定信号作为输出。我们可以将此信号映射到pll_not_locked
奴隶极光？如果是，会发生什么以及为什么？直到现在，这些引脚连接到主极光的pll_not_lick_out。（它是否正确？）我们可以将主极光的复位引脚连接到板复位引脚吗？或者我们可以连接gt_reset
引脚到板复位？或者两者兼而有之？我的主要问题是我需要数据意味着来自rs232或以太网的32位字，我需要同时通过极光将数据发送到其他板。没有处理器系统，我的逻辑正在工作。
我们尝试使用PS（处理器系统），我们无法完全同时发送单词。我们如何才能解决这个问题？在我的总体设计中，我有五个时钟，每个周期为10ns.1.SYSCLK连接到MB，Initclk
，drpclock2.Usetclk_out  - 来自Master aurora＆amp;连接到其他三个奴隶3.4.5.T
X_OUT_CLKs-来自三个从站 - 使用发送数据或接收数据我们可以使用单个时钟来进行整个设计来发送/接收包括PS的数据吗？如果是，哪个是最佳时钟？如果不是，我们如何解决这个问题？



以下为原文

Hi venkata
I need clarification
I want to use one quad say 117(GTXs-4).We are using Aurora protocol.Other end, we have separate four boards having single GTX each.Coming four GTXs board, I want to transmit data through 4 gtxs at same time.( all should send frame/single stream word at rising edge-starting point should be same).
How can we achieve this?
We tested so many cases.what we observed that some times it is working/some times its not.why?

In coming to quad,
One GTx is Master/with shared logic
Other 3-GTXs are slave/with out example design.
In block design, we mapped user clock from master to slaves, qpll lock out and sync clock, pll signal other as in data sheet.
How do we sync user clocks from all four GTXs?
We need to send data words at exactly same time to motherboard(my requirement).

Userclock is 10ns.

We added Microblaze to block design which has four auroras.my board board system clock us 10ns.
Some times u need to take data from Microblaze through BRAM or GPIO.
When we tried to take data from processor system and mapped to tx_data of aurora, we observed, that syncing is missed.
What could be the solution for the above?

Coming to microblaze system, we have clock wizard with locked signal as output.Can we map this signal to pll_not_locked of slave aurora?If yes, what will happen and why?
Till now, these pins are connected to pll_not_lick_out of master aurora.(Is it correct?)

Can we connect reset pin of master aurora to board reset pin?
Or Can we connect gt_reset pin to board reset ?
Or both?

My main problem is
I have to data means some 32 bit words from rs232 or Ethernet and I need to send data through auroras to other board at same time.

With out processor system ,my logic is working.when we tried with PS(processor system), we are not able to send words exactly same time.

How can we solve this problem?

In my total design, I have five clocks with period 10ns each.
1.SYSCLK-connected to MB,Initclk,drpclock
2.Usetclk_out - from Master aurora&connected to other three slaves
3.4.5.TX_OUT_CLKs-From three slaves-using transmit data or receive data

Can we use single clock to entire design to transmit/receive data including PS?

If yes, which is best clock?
If NO, how can we solve this?