大家好,
我正在将设计从STM8S105转移到STM8S207。
我正在考虑将时钟速度从最初的16MHz提高到24MHz,以便从核心获得更多的MIPS。
但是,对于时钟而言> 16 MHz,闪存需要1次等待。我想这些指令是由内核从闪存内取出的(即没有缓存)。
如果上述情况属实,则使用24 Mhz时钟核心运行速度会变慢。更快的时钟的唯一好处是更快的外设。
那是对的吗? (嗯,现在我想我应该用范围测试)
谢谢
尼科
以上来自于谷歌翻译
以下为原文
Hi all,
I'm moving a design from STM8S105 to STM8S207.
I'm thinking of raising the clock speed from originally 16MHz to 24 MHz in order to get more MIPS from the core.
However, for clocks > 16 MHz, the flash memory requires 1 waitsate. I suppose that the instruc
tions are fetched by the core from within the flash (i.e. there's no cache).
If the above is true, then the core would run slower with the 24 Mhz clock. The only benefit of a faster clock would be faster peripherals.
Is that correct? (Hm now I'm thinking that I should test that with a scope)
Thanks
Nico