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我知道我可以使用DCM来创建相对于彼此具有90度相移的4个时钟。
但我想创建4个时钟,每个时钟相对于彼此具有60度相移。 是否可以使用一个DCM(我想使用只有2个DCMS的144tqg软件包)? 该手册给我的印象是我可以有60度的相移,但DCM的所有输出将相移60度,所以我将不得不使用4个DCM 为我的申请。 如果使用2个DCM无法做到这一点,还有其他方法可以实现吗? 先谢谢你 Papadimitriou Athanasios 以上来自于谷歌翻译 以下为原文 I know that I can use a DCM to create 4 clocks with 90 degrees phase shift with respect to each other. But I would like to create 4 clocks each having 60 degrees phase shift with respect to each other. Is it possible by using one DCM (I want to use the 144tqg package which has only 2 DCMS)? The manual gave me the impression that I can have a phase shift of 60 degrees but all the outputs of the DCM will be phase shifted by 60 degrees, so I would have to use 4 DCMs for my application. If it is not possible to do that using 2 DCMs, is there another way of achieving that? Thank you in Advance Papadimitriou Athanasios |
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嗨Papadimitriou,
我想知道将使用四个60°相移时钟。 你的威廉希尔官方网站 将爆裂四次然后暂停两个阶段,但也许这对某些事情有好处。 你确定你真的需要时钟吗? 也许你可以使用时钟启用工作。 这意味着使用高出六倍的时钟频率,因此它取决于您所需的系统时钟。 有一个很好的综合 Eilert 以上来自于谷歌翻译 以下为原文 Hi Papadimitriou, I wonder what will be the use of four 60° phaseshifted clocks. Your circuit will burst four times then pause for two phases, but maybe it's good for something. Are you sure you really need clocks? Maybe you can work as well using clock enables. This would mean to use a six times higher higher clock frequency and so it depends on your desired system clock. Have a nice synthesis Eilert |
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选项1 - 正如Eilert所建议的那样。
选项2-如果需要,Clk freq更小 - 使用DCM生成多个of3的高速clk(比如30次 - 它将取决于DCM的输入Clk频率和频率范围)并使用计数器威廉希尔官方网站 。 选项3 - 您正在使用哪个设备Spartan3 / Spartan3E / Spartan3A .......您刚才提到了您要使用的软件包 (我想使用只有2个DCMS的144tqg包)? 在同一个软件包中,您可以找到其他更高级别的设备,它具有4个DCM。 例如,XC3s250E在具有4个DCM的TQ144封装中是可用的。 山塔努 Shantanu Sarkarhttp://www.linkedin.com/pub/shantanu-sarkar/0/33a/335 以上来自于谷歌翻译 以下为原文 Option 1 - As suggested by Eilert. Option 2- If required Clk freq is less - Use DCM to generate a high speed clk in multiple of 3 (say 30 Times - It will depend on the Input Clk Freq and freq range of the DCM) and use a a counter circuit. Option 3 - Which device you are using Spartan3 / Spartan3E / Spartan3A ....... you have only mentioned about the package you want to use (I want to use the 144tqg package which has only 2 DCMS)? In the same package you can find out some other higher device which is having 4 DCM. e.g XC3s250E is avialable in TQ144 Package which has 4 DCM. Shantanu Shantanu Sarkar http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335 |
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谢谢您的反馈,
我需要生成这4个相移的相同频率时钟作为ASIC的输入,因此它只是我的一个规范而不是在FPGA内部使用。 频率:24MHz的 问题是(纠正我,如果我错了)我想使用Spartan 3AN,它在TQ144封装中只有2个DCMS(XC3S50AN) XC3S200AN仅采用BGA封装。 我对FPGA很新,所以请你解释一下你提到的高频计数器选项: 选项2-如果需要,Clk freq更小 - 使用DCM生成高 速度clk的倍数为3(比如30倍 - 这将取决于输入 Clk频率和DCM的频率范围)并使用计数器威廉希尔官方网站 。 以上来自于谷歌翻译 以下为原文 Thank you for your responses, I need to generate these 4 phase shifted same frequency clocks as inputs to an ASIC, so it is just a spec for me and not for use inside the FPGA. frequency:24MHz The problem is (correct me if I am wrong) that I want to use the Spartan 3AN which in the TQ144 package has only 2 DCMS (XC3S50AN) The XC3S200AN is only BGA packeged. I am fairly new to FPGAs so could you please explain to me the high frequency- counter option you mentioned: Option 2- If required Clk freq is less - Use DCM to generate a highspeed clk in multiple of 3 (say 30 Times - It will depend on the InputClk Freq and freq range of the DCM) and use a a counter circuit. |
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这不是一个很好的解决方案。
但如果你没有得到任何时间问题,它可以解决。 我正在编写一个模型程序供您理解。 实体PS是 端口(Clk:在STD_LOGIC; RST:在STD_LOGIC中; Q0:输出STD_LOGIC; Q60:输出STD_LOGIC; Q120:输出STD_LOGIC; Q180:输出STD_LOGIC); 结束PS; 建筑行为的PS是 信号sQ0,sQ60,sQ120,sQ180:Std_Logic; 开始 P:过程(Clk,RSt) 变量计数:std_logic_vector(1 downto 0):=“00”; 开始 如果(rst ='0')那么 数:=“11”; SQ0 SQ0 SQ60 sQ120 SQ0 Shantanu Sarkarhttp://www.linkedin.com/pub/shantanu-sarkar/0/33a/335 以上来自于谷歌翻译 以下为原文 This is not a very good solution. But it can work out if you are not getting any timing issues. I am writing a model program for your understanding. entity PS is Port ( Clk : in STD_LOGIC; RST : in STD_LOGIC; Q0 : out STD_LOGIC; Q60 : out STD_LOGIC; Q120 : out STD_LOGIC; Q180 : out STD_LOGIC);end PS;architecture Behavioral of PS isSignal sQ0,sQ60,sQ120,sQ180 : Std_Logic;beginP: Process(Clk,RSt)Variable Count : std_logic_vector(1 downto 0) := "00";BeginIf(rst = '0') thenCount := "11";sQ0 <= '0';sQ60 <= '0';sQ120 <= '0';sQ180 <= '1';Else If(Rising_edge(Clk)) thenCount := Count + '1';if(Count = "11") then Count := "00";End If;case (Count) is when "00" =>sQ0 <= Not sQ0;sQ180<= Not sQ180;when "01" =>sQ60 <= Not sQ60;when "10" =>sQ120 <= Not sQ120;when others =>sQ0 <= '0';sQ60 <= '0';sQ120 <= '0';sQ180 <= '1';end case; End If;End If;End Process;Q0 <= sQ0;Q60 <= sQ60;Q120 <= sQ120;Q180 <= sQ180;end Behavioral; Shantanu Sarkar http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335 |
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嗨Papadimitriou,
shantanu已经向您展示了如何生成信号。 但是你要将这些信号输入ASIC并称之为时钟这一事实让我怀疑。 由于信号通过IOB然后通过PCB,并且没有真正的反馈,您可能会遇到一些问题。 好的,对于今天的技术来说,24MHz几乎是DC,但它仍然取决于ASICS的要求是否有效。 注意抖动,路由延迟和IO-Slewrate等引起的小相移。 您可以尝试一下,如果它能够工作就很开心,或者再次检查ASIC的要求,如果需要高精度,那么您可以使用特殊的时钟生成芯片。 有一个很好的综合 Eilert 以上来自于谷歌翻译 以下为原文 Hi Papadimitriou, shantanu already showed you how to generate the signals. But the fact that you are about to feed these signals into an ASIC and call them Clock makes me suspicious. Since the signals are going through the IOBs and then over the PCB, and theres no real feedback you may get some problems. Ok, 24MHz is nearly DC for todays technology, but it still depends on the ASICS requirements wether it works or not. Be aware of Jitter, small phase shifts caused by routing delay and IO-Slewrate etc.. You may give it a try, and be happy if it works, or check the ASICs requirement once more and if high accuracy is required maybe you are better of with a special clock generating chip. Have a nice synthesis Eilert |
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