如何分析传统乘法器和vedic乘法器的时序延迟？

如果你喜欢edk。
只需添加一个xps计时器并通过在你的代码的开头和结尾放置适当的API来测量时间



以下为原文

if u r in edk. just add an xps timer and measure time by placing proper API at the begining and end of ur code

嗨，
它是硬件解决方案吗？
那么它可能是一些顺序威廉希尔官方网站 。
你应该知道那个威廉希尔官方网站 的latencys，因为它们是由设计定义的。
合成报告或时序分析器（后者更可靠）为您提供威廉希尔官方网站 可以达到的最大时钟频率的数字。
这将是一些奇数，你可能会选择一些有意义的时钟频率。
（例如，如果Fmax = 162.743 MHz，您可以选择150MHz用于实际实施）
然后，您只需将延迟与时钟周期相乘，即可获得算法的持续时间。
某些算法具有可变延迟，这取决于处理的数据。
然后，您可以计算最低和最高延迟，以获得最小和最大持续时间。
有一个很好的综合 
Eilert



以下为原文

Hi,
is it a hardware solution?
Then it will probably be some sequential circuit.
You should know about the latencys of that circuit, because these are defined by design.
The synthsis report or the timing analyzer (the later one is more reliable) give you a number for the maximum clock frequency that circuit can reach.
This will be some odd number, and you might choos some meaningful clock frequency below that.
(e.g. if Fmax = 162.743 MHz, you might choose 150MHz for your actual implementation)
 
Then you just multiply the latency with the clock period and get the duration of the algorithm.
Some algorithms have a variable latency that depends on the processed data.
Then you can do the calculation for the lowest and highest latency to get the minimum and maximum durations.
 
Have a nice synthesis
   Eilert
 

谢谢你的回复。是的它是硬件解决方案。我无法理解你想在这里指出什么“这将是一些奇数，你可能会选择一些有意义的时钟频率。（例如，如果Fmax = 162.743 MHz，你
可能会选择150MHz用于实际实现）“。你能详细说明吗。因为我是学生所以我只有免费版的Xilinx ISE Design Suite 12.1和我一起。是否有可能检查时序分析器的报告（免费版）？



以下为原文

Thanks for response.
Yes it s a hardware solution.I can't understand what exactly you want to point here
"This will be some odd number, and you might choos some meaningful clock frequency below that.
(e.g. if Fmax = 162.743 MHz, you might choose 150MHz for your actual implementation)".
Could you plz elaborate it.As I am student so I only have free version of Xilinx ISE Design Suite 12.1 with me.Is it possible to check report on timing analyzer(free version)?

嗨，
webpackl仅限于它可以处理的设备大小和模拟器容量。
综合报告出现在控制台输出中，之后也可以进行检查。
您可以从摘要窗口中列出的所有报告中选择它，也可以使用文本编辑器以项目目录的形式轻松打开* .syr文件。
实施工具中提供静态时序分析。
它更准确，因为它考虑了实际的布局和布线，因此处理起来要复杂一些。
在综合报告中，您可能会发现以下部分：
时序摘要：---------------速度等级：-3最小周期：2.644ns（最大频率：378.201MHz）时钟前的最小输入到达时间：2.198ns时钟后的最大输出所需时间
：2.072ns最大组合路径延迟：1.350ns
你发现Fmax为378.201MHz。
现在，谁会在真正的威廉希尔官方网站 板上使用如此有趣的频率？
相反，人们可能会选择普通的300MHz。
然后，这应该用作计算的基础。
有一个很好的综合 
Eilert



以下为原文

Hi,
the webpackl is only limited in the size of devices it can handle and the simulators capacity.
 
The synthesis report appears in teh console output and can also be inspected afterwards.
You can select it from all the reports listed in the summary window or simly open the *.syr file in your project directory with a text editor.
 
The static timing analysis is available among the implementation tools.
It is more accurate since it takes the actual placement and routing into account, therefore it's a little more complex to handle.
 
In the synthesis report you might find some section like this:
Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 2.644ns (Maximum Frequency: 378.201MHz)
   Minimum input arrival time before clock: 2.198ns
   Maximum output required time after clock: 2.072ns
   Maximum combinational path delay: 1.350ns
 
There you find Fmax as 378.201MHz.
Now, who would use such a funny frequency on a real board?
Instead one might go for plain 300MHz.
Then this should be used as the base for your calculations.
 
Have a nice synthesis
  Eilert

谢谢eilert，你让我的综合非常简单。
我在摘要报告中找到了这个。
时序摘要：---------------速度等级：-5最小周期：3.418ns（最大频率：292.569MHz）时钟前的最小输入到达时间：4.721ns时钟后的最大输出所需时间
：8.273ns最大组合路径延迟：6.582ns
所以现在计算算法的持续时间。我该怎么办？
将此Fmax乘以8MHz（我的FPGA套件上的时钟），并将其反转以查找算法的时间段？我想我做错了。请指导。



以下为原文

Thanks eilert,you are making my synthesis really simple.
I found this in summary report.
 
Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.418ns (Maximum Frequency: 292.569MHz)
   Minimum input arrival time before clock: 4.721ns
   Maximum output required time after clock: 8.273ns
   Maximum combinational path delay: 6.582ns
 
So now to calculate the duration of algorithm.What I should do??
Multiply this Fmax with 8MHz(Clock on my FPGA Kit) and take its inverse to find the time period of my algorithm?I guess I am doing something wrong.Please guide.

嗨，
你错过了计算算法延迟的步骤。
执行操作需要多少个时钟周期？
（如果不确定你可以看看模拟并计算那里的时钟周期。但这是一些乏味的方式......）
这也取决于你想知道什么。
您是否希望获得某些设计以几乎全速运行的数字（如综合报告中所估算的）来估算可能的数据吞吐量，
或者你想为你的实际实现（使用8Mhz）计算它。
实际上，您始终可以计算您正在使用的时钟速率的延迟独立性。
这样您就可以获得算法质量的度量，
如有必要，此数字可以乘以之后的实际时间。
实际的定时信息仅对某些特定实现和与其他系统的接口有关。
或者让我以另一种方式贬低：
当使用“几乎DC”时，即使是某些算法的所有可能实现中最好的也无法执行任何操作（当谈论FPGA时，这将是8MHz的良好描述）。
那么，你要计算什么？
您想要将您的vedic算法与某些标准进行比较。
implemetation。
第一步是比较延迟。
减少延迟=更好的算法。
但如果执行得当，一个好的算法就没用了。
可以从综合报告中得出实施质量的度量。
（在S3设备上，大约300MHz的Fmax是一个非常好的结果。）
为了比较算法，您可以简单地忽略威廉希尔官方网站 板运行的8MHz时钟。
它只是你的威廉希尔官方网站 板的无用常量，并没有帮助估计某些算法的潜力。
有一个很好的综合 
Eilert



以下为原文

Hi,
you missed the step of calculationg the latency of your algorithm.
How many clock cycles are needed to perform an operation?
(If unsure you can alwas look at the simulation and count the clock cycles there. But that's some tedious way...)
 
Also it depends on what you want to know.
Do you want to get the number for some design running at almost full speed (as estimated in the synthesis report) to estimate the possible data throughput,
or do you want to calculate it for your actual implementation (which uses 8Mhz).
 
Actually you can always calculate the latency indepentent of the clock rate you are using.
This way you get a measure for your algorithm quality,
 
This number can be multiplied by the actual period afterwards, if necessary.
The actual timing information is only of interest for some specific implementation and interfacing stuff to other systems.
 
Or let it me prase in another way:
Even the best of all possible implementations of some algorithm can not do anything performant when clocked with "almost DC" (which would be a good description for 8MHz when talking about FPGAs these days).
So, what are you about to calculate?
 
You want to compare your vedic algorithm against some std. implemetation.
The first step would be to compare the latencies. Less latency = better algorithm.
But a good algorithm is useless if badly implememted. a measure of the implementation quality can be derived from the synthesis report. (Where an Fmax of roughly 300MHz on a S3 device is a quite good result.)
For the purpose of comparing algorithms you can simply ignore the 8MHz clock that your board runs with.
It's just a useless constant of your board and does not help estimating the potential of some algorithm.
 
 
 
Have a nice synthesis
  Eilert