后标准是否能够反映船上的FPGA测试？

在Vivado中，KEEP_HIERARCHY xdc约束支持有限。
在2012.4中，它可以应用于（design和debug_core）对象。
这限制了它用于控制完整设计和Chipscope debug_cores的层次优化（展平）。
由于此限制，使用xdc约束无法控制各个分层模块。
为了逐个模块地控制KEEP_HIERARCHY的值，请使用属性的rtl版本。
这可以在Vivado综合指南的第37页找到：http：//www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug901-vivado-synthesis.pdf KEEP_HIERARCHY RTL约束具有不同的优先级，具体取决于它们的位置
应用。
在模块声明和同一模块的实例化上使用该属性时，实例化属性将优先使用并由Vivado Synthesis使用。
这可以用于覆盖约束。
Vivado Synthesis中KEEP_HIERARCHY属性的另一个限制是它没有向实施工具进行前向注释。
这意味着实现工具将优化在综合期间保持完整的层次结构。
顺便说一句，应该使用“dont_touch”属性来代替KEEP_HIERARCHY属性。
“dont_touch”属性被转发注释到实现工具，因此将通过实现保留层次结构。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

In Vivado, the KEEP_HIERARCHY xdc constraint has limited support. in 2012.4 it can be applied to (design and debug_core) objects. This limits its use to control of hierarchy optimization (flattening) to the full design and Chipscope debug_cores. Due to this limitation, individual hierarchical modules are not controllable using the xdc constraint. In order to control the value of KEEP_HIERARCHY on a module by module basis, please use the rtl version of the attribute. This can be found on page 37 of the Vivado Synthesis Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug901-vivado-synthesis.pdf

The KEEP_HIERARCHY RTL constraint has different priorities depending on where they are applied. When using the attribute on both a Module declaration and an instantiation of that same module, the instantiation attribute will take precedence and be used by Vivado Synthesis. This can be used to override constraints.



Another limitation of the KEEP_HIERARCHY attribute in Vivado Synthesis is that it is not forward annotated the Implementation tools. This means that the Implementation tools will optimized the hierarchy that has been kept intact during synthesis. Going foward, the "dont_touch" attribute should be used in place of the KEEP_HIERARCHY attribute. The "dont_touch" attribute is forward annotated to the Implementation tools, so the hierarchy will be preserved through Implementation.

Thanks and Regards
Balkrishan
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XDC支持DONT_TOUCH但KEEP_HIERARCHY和KEEP不支持。使用KEEP_HIERARCHY的DONT_TOUCH实例和KEEP .. XDC示例：set_property DONT_TOUCH true [get_cells u1]
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

DONT_TOUCH is supported in XDC but KEEP_HIERARCHY and KEEP are not.

Use DONT_TOUCH instread of KEEP_HIERARCHY and KEEP.


. XDC Example: set_property DONT_TOUCH true [get_cells u1]Thanks and Regards
Balkrishan
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嗨巴尔克里斯，
你是说使用Vivado能够保持层次结构吗？
或者，让后标准模拟与FPGA板上的结果相同会更容易吗？
有点困惑的是他的DONT_TOUCH。
在XDC中，它不能使用KEEP_HIERARCHY？
DONT_TOUCH应该与KEEP_HIERARCHY的功能不同。
彼得昌



以下为原文

 
Hi Balkris,
 
Do you mean that using Vivado is able to keep the hierarchy?  Or, it is going to be easier to let the post-par simulation be the same as the result on the FPGA board?  A little confused about hte DONT_TOUCH.  In XDC, it can't use KEEP_HIERARCHY?  DONT_TOUCH is supposed to be different from the function of KEEP_HIERARCHY.
 
 
 
Peter Chang

嗨彼得
Synplify提供2个属性来管理层次结构，syn_netlist_hierarchy和syn_hier。
当EDIF网表中的true maintainhierarchy时，syn_netlist_hierarchy属性。
当为0时，给出一个扁平的网表（虽然合成可能仍然是维持层次结构）。
syn_hier是合成期间的控制层次结构边界。
syn_hier_netlist不影响合成，只影响合成的输出。
虽然syn_hier影响合成，因此可能输出EDIF文件。
检查此AR。
这可能会有所帮助。
http://www.xilinx.com/support/answers/17693.htm
问候
Sikta



以下为原文

Hi Peter
Synplify provides 2 attributes to manage hiearchy, syn_netlist_hierarchy
and syn_hier. The syn_netlist_hierarchy attribute when true maintains
hierarchy in the EDIF netlist. When 0, gives a flattened netlist (though
synthesis may still be maintaining hierarchy). The syn_hier is controls
hierarchy boundaries during synthesis. The syn_hier_netlist does not
affect synthesis, just the output from synthesis. While syn_hier affects
synthesis, and hence, maybe the output EDIF file.
 
Check this AR. This might be helpful.
http://www.xilinx.com/support/answers/17693.htm
 
Regards
Sikta

嗨西卡，
感谢你的信息。
如何将属性添加到synplify？
将它添加到.prj中？
谢谢。
set_option -syn_netlist_hierarchy是的
彼得昌



以下为原文

Hi Sikta,
 
Thanks for your information.  How to add the attribute into synplify?
Adding it into the .prj?  Thanks.
 
set_option -syn_netlist_hierarchy true
 
 
 
 
 
Peter Chang

synplify GUI中应该有选项。
否则你也可以提供RTL，
1
Verilog -------模块block_A（）/ *综合syn_hier =“firm”* /;
2
VHDL ---- VHDL：属性syn_hier：string; block_A的属性syn_hier：architecture是“firm”;
3
SDC --- define_attribute {U1} syn_hier {firm}



以下为原文

There should be option in synplify GUI. Otherwise you can provide in RTL also,
 
1

Verilog
-------

module block_A () /* synthesis syn_hier = "firm" */;
2

VHDL
----

VHDL:
attribute syn_hier: string;
attribute syn_hier of block_A : architecture is "firm";
3

SDC
---

define_attribute {U1} syn_hier {firm}

亲爱的Siktap，
谢谢。
让我尝试。
彼得



以下为原文

Dear Siktap,
 
Thank you.  Let me try.
 
 
Peter