【Z-turn Board试用体验】+试用PL

本帖最后由 blackroot 于 2015-6-10 17:06 编辑

一直没搞懂PS怎样给PL提供复位和时钟，今天这个问题终于解决了~~~~~用一个简单的例子来说明一下，怎样使用PS输出的时钟和复位信号：三色流水灯
配置PS部分就不用图说明了，方法和前面的一样，在其中勾选FCLK_CLK0、FCLK_RESET0_N
生成顶层例化代码
`timescale 1 ps / 1 ps

module system_wrapper
(FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
pl_clk,
rst_n);
  inout [53:0]FIXED_IO_mio;
  inout FIXED_IO_ps_clk;
  inout FIXED_IO_ps_porb;
  inout FIXED_IO_ps_srstb;
  output pl_clk;
  output rst_n;

  wire [53:0]FIXED_IO_mio;
  wire FIXED_IO_ps_clk;
  wire FIXED_IO_ps_porb;
  wire FIXED_IO_ps_srstb;
  wire pl_clk;
  wire rst_n;

system system_i
   (.FIXED_IO_mio(FIXED_IO_mio),
      .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
      .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
      .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
      .pl_clk(pl_clk),
      .rst_n(rst_n));
endmodule

新建verilog文件编写流水灯代码。
module led_flow(pl_clk,rst_n,led);
input pl_clk;//100Mhz
input rst_n;
output [2:0]led;
reg [2:0]led;
reg clk_100khz;
reg [9:0] count0;
reg clk_100hz;
reg [9:0]count1;
reg clk_1hz;
reg [6:0]count2;
always@(posedge pl_clk or negedge rst_n)
begin
if(!rst_n)
      count0<=10'd1;
      else if(count0<=10'd1000)

         count0<=count0+1;

      else count0<=10'd1;
end
always@(posedge pl_clk or negedge rst_n)
begin
if(!rst_n)
      clk_100khz<=0;
      else if(count0<=10'd500)
         clk_100khz<=1;
         else clk_100khz<=0;
end

always@(posedge clk_100khz or negedge rst_n)
begin
   if(!rst_n)
      count1<=10'd1;
      else if(count1<=10'd1000)
         count1<=count1+1;
      else count1<=10'd1;
  end

  always@(posedge clk_100khz or negedge rst_n)
  begin
if(!rst_n)
      clk_100hz<=0;
      else if(count1<=10'd500)
         clk_100hz<=1;
         else clk_100hz<=0;
end

always@(posedge clk_100hz or negedge rst_n)
begin
   if(!rst_n)
      count2<=7'd1;
      else if(count2<=7'd100)

         count2<=count2+1;

      else count2<=7'd1;
  end
  always@(posedge clk_100hz or negedge rst_n)
  begin
if(!rst_n)
      clk_1hz<=0;
      else if(count2<=7'd50)
         clk_1hz<=1;
         else clk_1hz<=0;
  end
always@(posedge clk_1hz or negedge rst_n)
begin
if(!rst_n)
      led[2:0]<=3'b110;//led[0]<=1
      else led[2:0]<={led[1:0],led[2]};
end
endmodule

重新例化顶层代码
module top(led_f,FIXED_IO_mio,FIXED_IO_ps_clk,FIXED_IO_ps_porb,FIXED_IO_ps_srstb);
output [2:0]led_f;
  inout [53:0]FIXED_IO_mio;
  inout FIXED_IO_ps_clk;
  inout FIXED_IO_ps_porb;
  inout FIXED_IO_ps_srstb;
// output pl_clk;
  //output rst_n;
wire clk;
wire reset;

system system_i
   (.FIXED_IO_mio(FIXED_IO_mio),
      .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
      .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
      .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
      .pl_clk(clk),
      .rst_n(reset));

led_flow led_flow_inst(.pl_clk(clk),
                     .rst_n(reset),
                     .led(led_f));
endmodule

生成bitstream下载到zynq，下载步骤open hardware manager->open target->open new target
然后一路NEXT到如下的界面