通过BAR和inbound region配置，
大致流程是：PCIE inbound端会对接收到的PCIE packet的PCIE BUS address和 BAR进行匹配，如果发现和其中某一个BAR一致，那么就按照该BAR对应的inbound region进行映射。具体流程你可以参考userguide，下面是2个例子，帮助理解：
Example 1: Inbound write, destination buffer 32KB in L2, 32-bit addressing
CMD_STATUS[IB_XLT_EN] = 1 (Inbound address translation enabled)
The target packets with PCIe address 0x9001_5678~0x9001_D677 (32KB) (Based on the previous Outbound Address Translation Example 1).
BAR1 = 0x9000_0000 (bits [3:0]=0000b, means 32-bit, non-prefetchable, memory BAR).
BAR1 Mask register is 0x00FF_FFFF. So BAR1 window size is 16MB.
BAR1 accepts this inbound write request since the window includes the PCIe address of the target packets.
IB_BAR0 = 1 (BAR1 is selected for IB Region 0)
IB_START0_HI = 0x0 (upper 32 bits are zero for 32-bit addressing)
IB_START0_LO= 0x9000_0000
IB_OFFSET0 = 0x1086_0000
Then the starting internal device address
= PCIe address – (IB_START0_HI:IB_START0_LO) + IB_OFFSET
= (0x9001_5678) – (0x9000_0000) + (0x1086_0000) = 0x1087_5678
Example 2: Inbound read, destination buffer 12MB in DDR, 64-bit addressing
CMD_STATUS[IB_XLT_EN] = 1 (Inbound address translation enabled)
The target packets with PCIe address 0x12345678_70000000~0x12345678_70BFFFFF (12MB) (Based on the previous Outbound Address Translation Example 2).
BAR2 = 0x7000000C (bits [3:0]=1100b, means 64-bit, prefetchable, memory BAR).
BAR3 = 0x12345678 (BAR3 Mask register is 0x0, non-masked)
BAR2 Mask register is 0x0FFF_FFFF. So BAR2&3 window size is 256MB.
BAR2&3 accept this inbound read request since the window includes the PCIe address of the target packets.
IB_BAR1 = 2 (BAR2&3 are selected for IB Region 1 for 64-bit addressing)
IB_START1_HI = 0x12345678 (upper 32 bits are zero for 32-bit addressing)
IB_START1_LO= 0x7000_0000
IB_OFFSET1 = 0x8700_0000
Then the starting internal device address
= PCIe address – (IB_START0_HI:IB_START0_LO) + IB_OFFSET
= (0x12345678_70000000) – (0x12345678_70000000) + (0x8700_0000)
= 0x8700_0000
So the data located in the buffer as 0x8700_0000~0x87BF_FFFF are fetched by the PCIe master port with PCIe address 0x12345678_70000000~0x12345678_70BFFFFF (no EDMA or CPU is involved in local device for the inbound transfer).
So the data packets with PCIe address 0x9001_5678~0x9001_D677 are transferred to the destination buffer as 0x1087_5678~0x1087_D677 by the PCIe master port (no EDMA or CPU is involved in local device for the inbound transfer).
通过BAR和inbound region配置，
大致流程是：PCIE inbound端会对接收到的PCIE packet的PCIE BUS address和 BAR进行匹配，如果发现和其中某一个BAR一致，那么就按照该BAR对应的inbound region进行映射。具体流程你可以参考userguide，下面是2个例子，帮助理解：
Example 1: Inbound write, destination buffer 32KB in L2, 32-bit addressing
CMD_STATUS[IB_XLT_EN] = 1 (Inbound address translation enabled)
The target packets with PCIe address 0x9001_5678~0x9001_D677 (32KB) (Based on the previous Outbound Address Translation Example 1).
BAR1 = 0x9000_0000 (bits [3:0]=0000b, means 32-bit, non-prefetchable, memory BAR).
BAR1 Mask register is 0x00FF_FFFF. So BAR1 window size is 16MB.
BAR1 accepts this inbound write request since the window includes the PCIe address of the target packets.
IB_BAR0 = 1 (BAR1 is selected for IB Region 0)
IB_START0_HI = 0x0 (upper 32 bits are zero for 32-bit addressing)
IB_START0_LO= 0x9000_0000
IB_OFFSET0 = 0x1086_0000
Then the starting internal device address
= PCIe address – (IB_START0_HI:IB_START0_LO) + IB_OFFSET
= (0x9001_5678) – (0x9000_0000) + (0x1086_0000) = 0x1087_5678
Example 2: Inbound read, destination buffer 12MB in DDR, 64-bit addressing
CMD_STATUS[IB_XLT_EN] = 1 (Inbound address translation enabled)
The target packets with PCIe address 0x12345678_70000000~0x12345678_70BFFFFF (12MB) (Based on the previous Outbound Address Translation Example 2).
BAR2 = 0x7000000C (bits [3:0]=1100b, means 64-bit, prefetchable, memory BAR).
BAR3 = 0x12345678 (BAR3 Mask register is 0x0, non-masked)
BAR2 Mask register is 0x0FFF_FFFF. So BAR2&3 window size is 256MB.
BAR2&3 accept this inbound read request since the window includes the PCIe address of the target packets.
IB_BAR1 = 2 (BAR2&3 are selected for IB Region 1 for 64-bit addressing)
IB_START1_HI = 0x12345678 (upper 32 bits are zero for 32-bit addressing)
IB_START1_LO= 0x7000_0000
IB_OFFSET1 = 0x8700_0000
Then the starting internal device address
= PCIe address – (IB_START0_HI:IB_START0_LO) + IB_OFFSET
= (0x12345678_70000000) – (0x12345678_70000000) + (0x8700_0000)
= 0x8700_0000
So the data located in the buffer as 0x8700_0000~0x87BF_FFFF are fetched by the PCIe master port with PCIe address 0x12345678_70000000~0x12345678_70BFFFFF (no EDMA or CPU is involved in local device for the inbound transfer).
So the data packets with PCIe address 0x9001_5678~0x9001_D677 are transferred to the destination buffer as 0x1087_5678~0x1087_D677 by the PCIe master port (no EDMA or CPU is involved in local device for the inbound transfer).
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