关于c6657 DDR3的问题

自己画的6657的板，发现DDR3初始化有问题，初始化参数是按照芯片手册来设置的，写数据进去会出错。初步怀疑是DDR3布线问题,请问ti的大神们，6657对DDR3的布线有什么具体的要求吗？或者是DDR3这一块要着重注意哪些方面。望详细赐教，谢谢！

DDR3时钟输入是50Mhz,输出时钟设置为
// +--------------------+---------------+--------+----------------------------+
// | DDR3 PLL VCO    | (CLKIN) Input |               
// | Rate (MHz)           | Clock (MHz)      | PLL2_M     PLL2_D |
// +--------------------+---------------+--------+----------------------------+
// | 1600                    | 50 (EVM)           | 31             | 1      |    
// | 1333                    | 50                      | 39             | 2      |
// | 1066                    | 50                      | 31             | 2      |
// +--------------------+---------------+--------+----------------------------+
这是我初始化时用的程序：
void BV6657_DDR3_Init()
[
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
    DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
    DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1

    DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15

    //From 4.2.1 Executing Partial Automatic Leveling -- Start
    DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
    //From 4.2.1 Executing Partial Automatic Leveling -- End

    //Values with invertclkout = 1
    /**************** Leveling Initialization Values ********************/
    DATA0_WRLVL_INIT_RATIO = 0x00;
    DATA1_WRLVL_INIT_RATIO = 0x00;
    DATA2_WRLVL_INIT_RATIO = 0x00;
    DATA3_WRLVL_INIT_RATIO = 0x00;
    DATA4_WRLVL_INIT_RATIO = 0x5F;
    DATA5_WRLVL_INIT_RATIO = 0x5F;
    DATA6_WRLVL_INIT_RATIO = 0x5B;
    DATA7_WRLVL_INIT_RATIO = 0x5A;
    DATA8_WRLVL_INIT_RATIO = 0x00;

    DATA0_GTLVL_INIT_RATIO = 0x00;
    DATA1_GTLVL_INIT_RATIO = 0x00;
    DATA2_GTLVL_INIT_RATIO = 0x00;
    DATA3_GTLVL_INIT_RATIO = 0x00;
    DATA4_GTLVL_INIT_RATIO = 0xA1;
    DATA5_GTLVL_INIT_RATIO = 0xA1;
    DATA6_GTLVL_INIT_RATIO = 0x88;
    DATA7_GTLVL_INIT_RATIO = 0x89;
    DATA8_GTLVL_INIT_RATIO = 0x00;

    DDR_PHYCTRL &= ~(0x00008000);
    DDR_PHYCTRL |= (0x00008000);
    DDR_PHYCTRL &= ~(0x00008000);

    DDR_SDRFC = 0x00003D08; // enable configuration

    DDR_SDTIM1 = 0x0CCF1623;
    DDR_SDTIM2 = 0x20867FDA;
    DDR_SDTIM3 = 0x557F881F;

    DDR_PHYCTRL = 0x0010010F;
    DDR_ZQCFG = 0x70074C1F;
    DDR_PMCTL = 0x0;
  //  DDR_SDRFC = 0x000007A1; // enable configuration

    DDR_SDCFG = 0x63437B32;
    TSC_delay_us(600);      //Wait 600us for HW init to complete


    DDR_SDRFC = 0x00000F42;       //Refresh rate = (7.8*500MHz)

    /**************** 4.2.1 Executing Partial Automatic Leveling ********************/

    RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

    RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value

    TSC_delay_us(30000);  //3ms
    //TSC_delay_us(30000);  //3ms

    printf("nDDR3 initialization is complete.n");
]