Virtex6路由不适合

我有一个SX475T，我已经对我设计的很大一部分进行了布局规划，但似乎我无法通过芯片的右下角以及右上角。
我有一个逻辑实例化了3次。
我在右上方放了一个pblock，垂直覆盖2个时钟区域。
下面是接下来的2个时钟区域中的第2个pblock（与第一个完全相同的逻辑）。
这正确地路由和解析。
然后我添加第三个副本并将其放在下面，并且任何一个地图都会失败，说没有空格或者标准杆具有数百万的计时分数。
我知道有足够的空间，因为其他2个pblock具有与源相同的NGC文件并且适合相同大小的块，。
我已经做了第三个pblock来覆盖所有剩余的时钟区域（大小加倍），它仍然说它不适合。
驱动和馈电的逻辑是在芯片的右侧中心，因此它应该到达底部以及顶部（相同的路径长度）。
物理资源估计表明，对于pblock，thsi pblock使用67％lut，52％ff（当我将pblock大小加倍时为1/2）
有没有一个隐藏的硅原因，右下角将更难以路由芯片的其余部分？
我认为xilinx曾经说过路由和右路是首选，但我不知道为什么，或者如果这仍然是真的。



以下为原文

I have a SX475T for which I have floorplanned a large part of my design but it appears I cant route to the bottom right corner of the chip as well as the top right.

I have one piece of logic that is instantiated 3 times. I put a pblock in the upper right that covers 2 clock regions vertically.  Below it is the 2nd pblock (exactly same logic as first) in the next 2 clockregions. This routes and pars correctly.  Then I add the 3rd copy and place it below that and either map fails saying there isn't space or par has a timing score in the millions.  I know there is enough space because the other 2 pblocks have the same NGC file as source and fit in the same size block, .  I have go as far as making the 3rd pblock to cover all the remaining clock regions (doubling the size) and it still says it wont fit.   The logic that drives and feeds this is in the right left side of the chip centered so it should reach the bottom just as well as the top (same path length). The physical resource estimation says thsi pblock uses 67%lut, 52%ff for the pblocks (1/2 that when I doubled the pblock size)

Is there a hidden silicon reason that the bottom right would be harder to route that the rest of the chip? I think xilinx used to say routing up and right was preferred but I don't know why, or if that's still true.