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[问答]

Cortex-MO+和M4之间的访问差异

大家好,我想问以下问题:皮质MO+与M4通路的区别。
1、在NPI中,PSoC 6可以在深度睡眠模式下访问WDT、SCB、比较器、波尔河、SCB,
并且可以在休眠模式下访问比较器和POR。
皮质Mo+和CordX-M4均可进入深睡眠模式下的WDT、SCB、比较器、波尔河、SCB;
可以在休眠模式下访问比较器和POR吗?
2、在PSOC6中只有CORTEX-M0+可以访问的区域或只有CORTEX-M4的区域可以访问吗?
RAM还是闪存?
3、1.2的问题的答案是否取决于微型计算机是否是PSoC 62
系列还是PSoC 63系列?
最好的问候
清水町

以上来自于百度翻译


     以下为原文
  Hello, I would like to ask the following questions on the difference between Cortex-MO + and M4 access.

1.It is stated in NPI that PSoC 6 can access WDT, SCB, Comparator, POR, SCB in Deep Sleep mode,
and can access Comparator and POR in Hibernate mode.The meaning of this description is that
Cortex-MO+ and Cortex-M4 both can access WDT, SCB, Comparator, POR, SCB in deep sleep mode,
and can access Comparator and POR in hibernate mode?

2.Are there areas that only Cortex-M0+ can access or areas that only Cortex-M4 can access in PSoC6's
RAM or FLASH?

3.Does the answer to the question of 1.2 change depending on whether the microcomputer is PSoC 62
series or PSoC 63 series?


Best Regards
Hiroaki Shimizu

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张帆

2018-11-28 16:36:41
你好,Hiroaki san,
对你的问题:
1。所有的外围设备都可以访问CM4和CM0+,因为它们共享相同的MMIO和内存地址空间。也就是说,你不能从CPU访问DeepSleep和Hibernate模式中的任何外围设备,因为在这些模式下你的CPU将被关掉。这些外设可以在DeepSleep和Hibernate系统中产生中断和唤醒CPU(M4或M0+或两者)(从Hibern唤醒)。ATE模式是一个系统复位事件,而不是CPU唤醒。
2。不,两个核心都可以看到整个寄存器空间。也就是说CM0+和CM4都有自己的ARM定义的系统空间寄存器(包括中断优先级、启用/禁用等寄存器)。这些寄存器只对访问它的内核可见。
三。不,在62和63个设备之间不重要。
让我知道这是否有帮助。
当做,
Meenakshi Sundaram R

以上来自于百度翻译


     以下为原文
  Hello Hiroaki-san,
 
To your questions:
1. All the peripherals are accessible to both CM4 and CM0+, as both share the same MMIO and Memory address space. That said, you cannot access any of these peripherals in DeepSleep and Hibernate modes from the CPU, as your CPU will be powered-off in these modes  These peripherals can generate interrupt and wakeup the CPU (either M4 or M0+ or both) in DeepSleep and the system in hibernate (as wakeup from hibernate mode is a system reset event not CPU wakeup).
 
2. No. Both the cores can see the entire register space. That said both CM0+ and CM4 have their own ARM defined system space registers (includes interrupt priority, enable/disable etc. registers). These registers are visible only to the core that access it.
 
3. No. It should not matter between 62 and 63 devices.
 
Let me know if this helps.
 
Regards,
Meenakshi Sundaram R
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黄远飞

2018-11-28 16:53:12
引用: 斯图尔特233 发表于 2018-11-28 08:37
你好,Hiroaki san,
对你的问题:
1。所有的外围设备都可以访问CM4和CM0+,因为它们共享相同的MMIO和内存地址空间。也就是说,你不能从CPU访问DeepSleep和Hibernate模式中的任何外围设备,因为在这些模式下你的CPU将被关掉。这些外设可以在DeepSleep和Hibernate系统中产生中断和唤醒CPU(M4或M0+或两者)(从Hibern唤醒) ...

你好,梅纳克什桑德拉姆
谢谢你的回答。
我可以再问你一个问题吗?
[问题]
你说“你不能从CPU中访问DeepSleep和Hibernate模式中的任何外围设备”
这是否意味着在休眠和休眠模式下输出到外围设备的API无效?
最好的问候
清水町

以上来自于百度翻译


     以下为原文
  Hello Meenakshi Sundaram R-san,
Thank you for answering.
May I ask you an additional question?
 
[Question]
You said "you cannot access any of these peripherals in DeepSleep and Hibernate modes from the CPU"
Does this mean that the API that is output to the peripheral during Deepsleep and Hibernate modes is invalid?
 
Best Regards
Hiroaki Shimizu
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张帆

2018-11-28 17:07:38
引用: cqeqw 发表于 2018-11-28 08:53
你好,梅纳克什桑德拉姆
谢谢你的回答。
我可以再问你一个问题吗?

我的意思是当你的CPU处于关闭状态时,当你处于睡眠状态或休眠模式时,你不能执行代码(访问外围设备)。
外围设备能够在DeepSleep /Hibernate模式下运行,如果它们被配置并支持在这些模式下运行。
所以,在DeepSleep /Hibernate模式下的外围操作是的。
在睡眠/ DeepSleep /休眠模式下的CPU操作(因此访问)-不。

以上来自于百度翻译


     以下为原文
  What I meant is you cannot execute code (that access the peripheral) when you are in DeepSleep or Hibernate mode  as your CPU is OFF
 
The peripheral is capable of operating in DeepSleep/Hibernate modes, if they are configured and support to run in those modes.
 
So, peripheral operation in DeepSleep/Hibernate modes - Yes.
CPU operation (hence access) in Sleep/DeepSleep/hibernate modes - No.
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