FX2以EP Full标志怎么设置开始

嗨，Ali，
使用的端点配置是什么，端点使用和它们的缓冲。很可能你并没有正确地配置它们。另一件事是，你是通过在VFET序列之后写0x80到EXBCL寄存器来终结端点。
问候，阿南德



     以下为原文
  Hi Ali,
    What is the endpoint configuration you're using,
Endpoints used and their buffering. Most probably you're not configuring them right. One other thing is, are you arming OUT endpoints by writing 0x80 to the EPxBCL register after the FIFORESET sequence.
    Regards,
Anand

设置端点的初始化代码：
无效的用户（）
{
EA＝0；/ /中断禁用-简化调试和设置时间
IFCONFIG＝0xE3；SycDelayle（）；//内部，48 MHz，同步，从
ReVCTL= 0x03；SycDelay.（）；
//设置调试端点
EP1OutCFG= 0xB0；SycDelay.（）；/ /中断
EP1CIFFG＝0xB0；SycDelay.（）；
ReARMEP1（）；
/init标志。在DOCS/FPGA-CyPACTET.TXT中列出
pFrAGSABA= 0x8C；SycDelay.（）；
pFrAgCSCD= 0x09；SycDelay.（）；
//FIFONIOLID= 0x00；SycDelay.（）；
//设置LED输出，并照亮它
PTCCFG＆AMP= ~0x80；
OEC＝0x80；
SycDelay.（）；
PC7＝1；
/整理FIFO
//参阅：HTTP//www-RelabalCalp/Cu/EnEnt/Engut/St/6142-2-1.PHP
/CyPress芯片和“全”旗在暖启动时发出
EP2CFG＝0xE4；SycDelay.（）；
EP4CFG＝0xA2；SycDelay.（）；
EP6CFG= 0x00；SycDelay.（）；
EP8CFG＝0x00；SycDelay.（）；
FiPosie= 0x80；SycDelay.（）；
FiPosit＝0x82.；
FiPosit＝0x84. SycDelay.（）；
FiPosit＝0x86.
FiPosit＝0x88；SycDelay.（）；
FiPosie= 0x00；SycDelay.（）；
OutpkStay= 0x84. SycDelay.（）；
OutpkStay= 0x84. SycDelay.（）；
IpkChans= 0x82.；
IpkChans= 0x82.；
EP2FIFOCFG＝0x00；SycDelayy（；）/ /以确保它看到0和1的过渡。
EP4FIFOCFG＝0x00；SycDelay.（）；
EP2FIFOCFG＝0x0b；SycDelay.（）；
EP4FIFOCFG＝0x11；SycDelay.（）；
EP2AutoLunh＝0x01；SycDelay.（）；
EP2AutoLeNLL＝0x00；SycDelay.（）；
EA＝1；
}



     以下为原文
   My initialisation code for setting endpoints:
     
    void init_user()
    {
  EA = 0; //Interrupts disabled - simplify debugging and setup times
 
  IFCONFIG = 0xE3; SYNCDELAY(); //internal, 48MHz, SYNC, slave
  REVCTL = 0x03; SYNCDELAY();
 
  //Setup debug endpoints
  EP1OUTCFG = 0xB0; SYNCDELAY(); //Interrupt
  EP1INCFG = 0xB0; SYNCDELAY(); 
  REARMEP1OUT();
 
   //init flags. listed in docs/fpga-cypacket.txt
  PINFLAGSAB = 0x8C; SYNCDELAY();
  PINFLAGSCD = 0x09; SYNCDELAY();
  //FIFOINPOLAR = 0x00; SYNCDELAY();
 
  //Setup LED output, and light it
  PORTCCFG &= ~0x80;
  OEC |= 0x80;
  SYNCDELAY();
  PC7 = 1;
 
  //Sort out FIFOs
  //see: http://www.embeddedrelated.com/usenet/embedded/show/65142-1.php
  //Issue with cypress chip and 'full' flag on a warm start
  EP2CFG = 0xE4; SYNCDELAY();
  EP4CFG = 0xA2; SYNCDELAY();
  EP6CFG = 0x00; SYNCDELAY();
  EP8CFG = 0x00; SYNCDELAY();
 
  FIFORESET = 0x80; SYNCDELAY();
  FIFORESET = 0x82; SYNCDELAY();
  FIFORESET = 0x84; SYNCDELAY();
  FIFORESET = 0x86; SYNCDELAY();
  FIFORESET = 0x88; SYNCDELAY();
  FIFORESET = 0x00; SYNCDELAY();
 
  OUTPKTEND = 0x84; SYNCDELAY();
  OUTPKTEND = 0x84; SYNCDELAY();
  INPKTEND = 0x82; SYNCDELAY();
  INPKTEND = 0x82; SYNCDELAY();
 
  EP2FIFOCFG = 0x00; SYNCDELAY(); //to ensure it sees a 0->1 transition
  EP4FIFOCFG = 0x00; SYNCDELAY();
 
  EP2FIFOCFG = 0x0B; SYNCDELAY();
  EP4FIFOCFG = 0x11; SYNCDELAY();
 
  EP2AUTOINLENH = 0x01; SYNCDELAY();
  EP2AUTOINLENL = 0x00; SYNCDELAY();
 
  EA = 1;
}

Ali
您正在使用一个无效的端点配置。请查看12个有效端点配置的最新TRM的第30页。此外，如果不使用端点，不要写入其EXCFCFG寄存器来禁用它。如果未使用端点，则应避免向与其对应的寄存器写入。
EP2CFG＝0xE4？？？？这个说法似乎也是错误的。
问候，阿南德



     以下为原文
  Ali,
    You're using an invalid endpoint configuration. Please look at page 30 of the latest TRM for the 12 valid endpoint configurations. Also if you're not using a endpoint do not write to its EPxCFG register to disable it. If an endpoint is not being used you should avoid writing to registers corresponding to it.
    EP2CFG = 0xE4???? This statement also seems wrong.
    Regards,
Anand

对不起，我本应该发现的。我已经把它改为使用11型（EP2 1024×3 +EP8 512×2）：
FB；SycDelay[（）；Ep6CFG= 0x00；SycDelay-（）；Ep8CFG= 0xA0；SycDelay.（；FiPosie= 0x80；SycDelay.）；FippeTe= 0x82.；SycDelay.（；）FiPosie= 0x84.；SycDelay.（；），FippeTe= 0x86；SycDelay.（；）EP2CFG＝0XX88；SycDelay-（）；OpkkTale= 0x82.；SycDelay-（；）；PkkTale= 0x82.；SycDelay-（；）；PykTyrase= 0x82.；SycDelay.（；）EP2FIFOFFG＝0x00；SycDelayy（；）/ /以确保它看到一个0和1的过渡EP8FIFOCFG＝0x00；SycDelaye（）；EP2FIFOCFG＝0x0b；SycDelay.（）；EP8FIFOFFG；UTPKTACEE= 0= 0x11；SycDelay-（）；EP2AutoLunh＝0x01；SycDelayle（）；EP2AutoLunl＝0x00；SycDelay-（）；EP不再看起来标记为“满”，但我仍然无法与FX2通信。在发送2个包（填充缓冲区）之后，我得到超时，并且在2次读取尝试之后（我想它应该在3次缓冲之后），我得到超时。还有什么意见吗？



     以下为原文
   Sorry, I should have spotted that. I have changed it to use type 11 (EP2 1024*3 + EP8 512*2):
      EP2CFG = 0xFB; SYNCDELAY();   EP4CFG = 0x00; SYNCDELAY();   EP6CFG = 0x00; SYNCDELAY();   EP8CFG = 0xA0; SYNCDELAY();    FIFORESET = 0x80; SYNCDELAY();   FIFORESET = 0x82; SYNCDELAY();   FIFORESET = 0x84; SYNCDELAY();   FIFORESET = 0x86; SYNCDELAY();   FIFORESET = 0x88; SYNCDELAY();   FIFORESET = 0x00; SYNCDELAY();    OUTPKTEND = 0x88; SYNCDELAY();   OUTPKTEND = 0x88; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();    EP2FIFOCFG = 0x00; SYNCDELAY(); //to ensure it sees a 0->1 transition   EP8FIFOCFG = 0x00; SYNCDELAY();    EP2FIFOCFG = 0x0B; SYNCDELAY();   EP8FIFOCFG = 0x11; SYNCDELAY();    EP2AUTOINLENH = 0x01; SYNCDELAY();   EP2AUTOINLENL = 0x00; SYNCDELAY();  The EP's no longer seem to be coming up marked as full anymore, but I am still unable to communicate with the FX2). After sending 2 packets (which fills the buffer), I get timeouts, and after 2 read attempts (I would have thought it should be after 3 since triple buffering), I get timeouts. Any more comments?   

Ali
如前所述，当不使用特定端点时，避免向对应于它的寄存器写入。
尝试删除线条
EP4CFG＝0x00
EP6CFG= 0x00
应该解决这个问题。
当做，
阿南德



     以下为原文
  Ali,
    As stated before, When you are not using a particular endpoint avoid writing to the registers corresponding to it.
    Try removing the lines
    EP4CFG = 0x00 and
    EP6CFG = 0x00
    It should resolve the issue.
    Regards,
    Anand

不，这也无济于事。
如果我删除这些链接，那么那些EPS认为它们是有效的（因此，假设内存分配出错了吗？）
如果我使用EP4CFG＆AMP:0x7F；为了确保有效位被清除，则它们不再被标记为有效，但我仍然得到与以前相同的连接性问题。
我没有问题EP1in /去-这是我用来提供回放的寄存器，试图帮助解决为什么，但我不知道为什么它不会让计算机访问FIFO？
当我把前2个包发送到EP8时，字节计数每次递增2（正确的是因为它们是2字节的分组），并且所有的子计数都被拒绝（双缓冲，所以这是预期的行为）。
一旦其中一个数据包被接收，EP2就被FPGA填充，BytCeNtt立即到达1024，但是我无法从这个EP中读取任何东西。AutoIn和AutoOutin和正在使用，如在先前的初始化中所示。
此外，由于某些原因，当FPGA读取EP8（我认为它读取数据包，因为它不提供任何输出，直到它得到一些数据包-这是它被编程来做什么），字节不能减少（它是指）吗？这就是为什么我不能再发送给那个EP了吗？）
谢谢。



     以下为原文
   Nope, that doesn't help either.
    If I remove those linse then those EPs think they are valid (so presumably memory allocation goes wrong?)
    If I use EP4CFG &= 0x7F; To ensure the VALID bit is cleared, then they are no longer marked as valid, but I still get the same connectivity issues as before.
    I had no problems getting EP1IN/OUT going - which I am using to provide readbacks of the registers to try to help work out why, but I have no idea why it won't let the computer access the FIFOs?
    When I send the first 2 packets to EP8, the byte count increments by 2 each time (correct because they are 2 byte packets), and all subsuquent ones get rejected (double buffering, so this is the expected behaviour).
    As soon as one of those packets gets received, EP2 gets filled by the FPGA, and the bytecount goes immediately to 1024, but I am unable to read anything out of this EP. AUTOIN and AUTOOUT and being used, as shown in the previous initialisation.
    Also, for some reason when the FPGA reads EP8 (well, I think it reads the packets, because it doesn't provide any output untill it gets some packets - which is what it is programmed to do), the bytecount doesn't decrement (is it meant to? is this why I can't send any more to that EP?)
    Thanks.

Ali
正如您已经知道的，端点缓冲器是由4个端点共享的，因此当您为配置配置时，预期寄存器写入将负责禁用当您这样做时不使用。奇怪的是，它不起作用。
长假后我回来了。所以我和我一起工作。给我一点时间，我查一下然后再回来。
当做，
阿南德



     以下为原文
  Ali,
    As you would already know the endpoint buffer is shared by the 4 endpoints so when you configure for a configuration the register write is expected to take care of disabling not being used when you do so. It is strange that it didn't work.
    I'm back after a long vacation. So I've boards with me to work on. Give me a little time I'll check on this and get back.
    Regards,
    Anand

嗨，Ali，
现在有更多的时间来看这个了。
发送2个数据包后，您将得到超时。你试过在把2个数据包读入FPGA之后（通过FX2LP的奴隶FIFO接口）发送数据包吗？
从FPGA发送到EP8的数据包有多少？如果你发送3，你应该能读3。如果你发送2，你只能阅读2。
当做，
阿南德



     以下为原文
  Hi Ali,
    Just now got more time to look at this.
    After sending 2 packets you're bound to get timeout. Have you tried sending packets after reading those 2 packets to the FPGA (through the Slave FIFO interface of FX2LP)?
    How many packets are you sending to EP8 from the FPGA. If you're sending 3, you should be able to read 3. If you send 2 you will be able to read only 2.
    Regards,
    Anand

我发送1个数据包（2字节）到EP8：没有超时。EP2BC＝0
FPGA阅读（我认为）。将数据发送到EP2。EP2BC & GT；0。
试着从PC中读取EP2：超时（和所有的尝试读取EP8）
再次发送：没有超时。
再次发送：超时。
一旦FPGA收到最初的控制命令，它将发送数据不断EP2（ep2bc直奔1024）在~ 48mhz直到它告诉ep2full。一旦它变空了，它将开始尝试再次发送。



     以下为原文
  I send 1 packet (2 bytes) to EP8: no timeout. EP2BC=0
    FPGA reads (I think). Sends data to EP2. EP2BC > 0.
    Try reading EP2 from PC: timeout (and all subsuquent attempts to read EP8)
    Send again: no timeout.
    Send again: timeout.
    Once the FPGA  receives its initial control commands, it will send data continuously to EP2 (EP2BC goes straight to 1024) at ~48MHz untill it gets told EP2FULL. Once it becomes empty, it will start trying to send again.

当TRM说（第100页）：
在同步模式下，SLRD和SLWR使IFCK时钟引脚成为可能。
这是否意味着，因为我有FX2安装来驱动iFCK引脚从内部的48 MHz时钟，即IFCK不是外部可见在这个引脚（对于外部主机），直到我采取SLRD或SLWR低？
谢谢。
阿里



     以下为原文
   When the TRM says (page 100):
    "In synchronous mode SLRD and SLWR are enables for the IFCLK clock pin".
    Does this mean that since I have the FX2 setup to drive the IFCLK pin from the internal 48MHz clock, that the IFCLK is not extervally visible on this pin (for the ext. master) until I take SLRD or SLWR low?
    Thanks.
    Ali

Ali
IFCK将永远是可见的，如果你已经配置它被输出。SLRD和SLWR是为IFCK引脚启用意味着它将合格的数据。因此，只有当它们被断言，总线才对IFCK数据进行采样。否则IFCK仍将切换，但总线不会被采样。
当做，
阿南德



     以下为原文
  Ali,
    IFCLK will always be visible if you've configured it for being outputted. SLRD and SLWR being enables for IFCLK pin means that it'll qualify the data. So only when they're asserted the bus is sampled for data with respect to the IFCLK. Otherwise IFCLK will still be toggling but the bus won't be sampled.
    Regards,
    Anand