如何约束内部生成的i2s o时钟？

嗨，我有一个小代码片段我试图穿上xilinx CPLD  -  xa2c128-7VQ100
mclk（24MHz）是设计的输入，从中生成i2s_o clk。
然后，i2s_o时钟进入设计中的其他一些小进程和输出引脚。
i2s_o时钟以下列方式生成 -
总是@（posedge mclk或negedge rst_n）开始if（！rst_n）i2s_o else i2s_o end
mclk不用于设计中的任何其他地方
当我在CPLD上实现设计时（使用ISE 14.1），我总是会收到警告 -
Cpld：310  - 无法应用tiMESPEC TS_mclk = PERIOD：mclk：41.666nS：HIGH：20.833nS，原因如下：（a）未找到信号名称;
（b）由于优化而删除或重命名的信号;
（c）TIMESPEC中的FROM节点和TO节点之间没有路径。
然而，ISE约束编辑器说上面的约束很好，有效且语法正确。
我的问题是 -
1）警告可以被忽略吗？
如果没有，我怎么能摆脱上述警告？
我只在CPLD实施的情况下看到它。
如果我将设备更改为virtex FPGA，警告就会消失
2）如何约束内部生成的i2s_o时钟？
在约束编辑器中，我没有看到内部的i2s_o clk但是我确实看到了一个i2s_o_OBUF clk（也许是因为它被路由到输出引脚？）。
既然i2s_o clk也进入了设计中的某些进程，那么仅限制i2s_o_OBUF时钟是否正确？
如果没有，我如何在约束编辑器中找到i2s_o时钟，或者这个时钟的约束语法应该如何？
请告诉我 ...
谢谢，
ž。



以下为原文

hi, i have a small code snippet im trying to put on a xilinx CPLD - xa2c128-7VQ100

mclk (24MHz) is an input to the design from which i2s_o clk is generated. the i2s_o clock then goes to some other small processes and an output pin in the design. i2s_o clock is generated in the following manner -
always @ (posedge mclk or negedge rst_n) begin
if (!rst_n)
    i2s_o <= 1'b0;
else
    i2s_o <= ~i2s_o;
end

mclk is not used anywhere else in the design

when i implement the design on the CPLD (using ISE 14.1), i always get a warning saying -

Cpld:310 - Cannot apply TIMESPEC TS_mclk =
PERIOD:mclk:41.666nS:HIGH:20.833nS because of one of the following: (a) a
signal name was not found; (b) a signal was removed or renamed due to
optimization; (c) there is no path between the FROM node and TO node in the
TIMESPEC.

however the ISE constraints editor says the above constraint is fine and valid and syntactically correct. My questions are -
1) can the warning be ignored? if not, how can i get rid of the above warning?
i only see it in case of CPLD implementation. if I change the device to a virtex FPGA, the warning goes away

2) how do i constraint the i2s_o clock which is generated internally?
in the constraints editor, i donot see the internal i2s_o clk however i do see an i2s_o_OBUF clk (maybe because it is routed to an output pin?).
since the i2s_o clk also goes to some processes inside the design, is it correct to just constraint the i2s_o_OBUF clock?

if not, how can i locate the i2s_o clock in the constraints editor or how should the constraint syntax for such a clock be?

please let me know ...

thanks,
z.