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如何计算Async Fifo Depth

嗨,
我想计算异步fifo的深度,但我很困惑如何计算它。
fifo参数如下:
写Clk Freq = 60 MHz。
读取Clk Freq = 100 MHz。
最大WriteBurst大小= 1024。
脉冲串写入之间的延迟= 4 clk。
ReadDelay = 2 clk。
任何人都可以帮助计算fifo深度的公式。
提前致谢...!

以上来自于谷歌翻译


以下为原文

Hi,
I want to calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows:
Write Clk Freq = 60 MHz.
Read Clk Freq = 100 MHz.
Maximum Write Burst Size = 1024.
Delay between writes in burst = 4 clk.
Read Delay = 2 clk.

Can anyone help with the formula for calculating the fifo depth.

Thanks in advance...!

回帖(9)

刘丰标

2019-4-17 08:39:17
嗨,
我想计算异步fifo的深度,但我很困惑如何计算它。
fifo参数如下:
写Clk Freq = 60 MHz。
读取Clk Freq = 100 MHz。
最大WriteBurst大小= 1024。
脉冲串写入之间的延迟= 4 clk。
ReadDelay = 2 clk。
任何人都可以帮助计算fifo深度的公式。
提前致谢...!

以上来自于谷歌翻译


以下为原文

Hi,
I want to calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows:
Write Clk Freq = 60 MHz.
Read Clk Freq = 100 MHz.
Maximum Write Burst Size = 1024.
Delay between writes in burst = 4 clk.
Read Delay = 2 clk.
 
Can anyone help with the formula for calculating the fifo depth.
 
Thanks in advance...! 
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潘晶燕

2019-4-17 08:46:26
检查以下链接,看看是否有帮助
http://forums.xilinx.com/t5/General-Technical-Discussion/FIFO-Depth-calculation/m-p/30903/highlight/true#M1313
--Krishna

以上来自于谷歌翻译


以下为原文

check the following link and see if this helps
 
http://forums.xilinx.com/t5/General-Technical-Discussion/FIFO-Depth-calculation/m-p/30903/highlight/true#M1313
 
--Krishna
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白桦

2019-4-17 08:52:03
K,
那你写的每5个60 MHz时钟呢?
你读的每3个100 MHz时钟?
写入速率为12 MHz(60/5)
读取速率为33.3 MHz(100/3)
你的阅读速度比你写的要快......
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

k,
 
So every 5 60 MHz clocks you write?
 
And every 3 100 MHz clocks you read?
 
Write rate is 12 MHz (60/5)
 
Read rate is 33.3 MHz (100/3)

You are reading faster than you are writing...
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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陈舒斌

2019-4-17 08:58:56
是的,我的阅读比写快,这就是为什么我很困惑如何计算深度。
那你写的每5个60 MHz时钟呢?
你读的每3个100 MHz时钟?
写入速率为12 MHz(60/5)
读取速率为33.3 MHz(100/3)
你如何得出上述结论。
我的写突发是1024,写突发之间的延迟是4 Wr_clk。
读延迟为2 Rd_clk。

以上来自于谷歌翻译


以下为原文

Yes my read is faster than write, thats why I am confused how to calculate the depth.
 
So every 5 60 MHz clocks you write?
 
And every 3 100 MHz clocks you read?
 
Write rate is 12 MHz (60/5)
 
Read rate is 33.3 MHz (100/3)
 
How do u come up with the above conclusion.
My write burst is 1024 and delay between write burst is 4 Wr_clk.
Read delay is 2 Rd_clk.
 
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