在VHDL中是否有任何Verilog`ifdef等效的例子？

vhdl没有宏语言，但它有泛型。
您可以将定义不存在视为泛型的默认值（比如0），如果泛型具有不同的值，则执行不同的操作。
这将允许您实例化不同版本的IP或在代码中具有不同的逻辑。
但是由于VHDL没有宏语言，你将无法使用#include之类的东西。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。
在原帖中查看解决方案



以下为原文

vhdl doesn't have a macro language but it has generics. You can treat a define  no existing as the default value of a generic (say 0) and take a different action if the generic has a different value. This would allow you to instantiate a different version of an IP or have different logic in your code. But you won't be able to use things like #include in there as VHDL doesn't have a macro language.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.View solution in original post

http://www.thecodingforums.com/threads/vhdl-has-no-define-like-verilog.24099/
Austin Lesea主要工程师Xilinx San Jose



以下为原文

http://www.thecodingforums.com/threads/vhdl-has-no-define-like-verilog.24099/
Austin Lesea
Principal Engineer
Xilinx San Jose

vhdl没有宏语言，但它有泛型。
您可以将定义不存在视为泛型的默认值（比如0），如果泛型具有不同的值，则执行不同的操作。
这将允许您实例化不同版本的IP或在代码中具有不同的逻辑。
但是由于VHDL没有宏语言，你将无法使用#include之类的东西。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

vhdl doesn't have a macro language but it has generics. You can treat a define  no existing as the default value of a generic (say 0) and take a different action if the generic has a different value. This would allow you to instantiate a different version of an IP or have different logic in your code. But you won't be able to use things like #include in there as VHDL doesn't have a macro language.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.