HDLC控制器的设计在哪里实施CDC

我正在设计一个HDLC接收器接口。
该接口看起来非常类似于SPI从器件，除了没有外部芯片选择进入。帧同步发生在数据中使用唯一的令牌。
因此有2个信号进入FPGA：
EXT_CLK：在我的情况下几兆
DIN：与EXT_CLK同步的数据
在同步和反序列化之后，数据被写入FIFO，供处理器使用。
我目前看到了2种设计策略，我希望您就他们之间的选择提出意见/建议/反馈，如果有更好的策略，我甚至会选择第3种策略。
随意评论一些或所有问题。
策略1：CDC使用异步FIFO
基本上整个串行接收系统（FSM +串行移位寄存器）在“外部时钟域”中实现。
双域FIFO负责时钟域交叉。
Q1：在我的应用程序中，EXT_CLK可以以不规则的方式断开连接/重新连接，EXT_CLK输入上有临时的“故障”→这可能会在使用此策略时将FSM置于未知状态？
策略2：CDC上的输入CLK和数据
在此策略中，传入的EXT_CLK和EXT_DIN被视为异步输入。
它们使用“CDC单”与时钟域交叉到内部FPGA时钟域（FPGA_CLK）。
时钟的CDC之后是边沿检测器，它在上升沿产生单个标记（宽度= 1 FPGA_CLK周期）。
一旦在CDC之后，FSM，移位寄存器和FIFO的两端都在同一时钟域上工作。
Q2：FPGA时钟应该比EXT_CLK_IN（因子）高一个因子才能工作，是否有一些'规则'表明它至少应该是4x，8x，......？
问题3：作为对此的直接结论，策略1可能以比策略2更高的EXT_CLK频率运行？
这就是网上大多数设计使用策略1的原因吗？
问题4：如果我在网上浏览并查看SPI从设备实现（找不到很多HDLC实现，并且SPI从设备接近这一点），我大多看到实现的第一个策略。
然而，这种将CDC单一放在输入信号上的策略对我来说似乎更加严格，特别是当EXT_CLK可以随机断开/重新连接时。
或者我在这里遗漏了什么？
问题5：我认为策略2的另一个优点是FSM可以在单个EXT_CLK周期内转换多个状态，因此在FSM实现中具有更多“灵活性”。
问题6：看起来策略2可能比策略1使用更高的功率，这是正确的吗？
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以下为原文

I'm designing a HDLC receiver interface. This interface looks very similar to an SPI slave, except that there's no external chip select coming in. Frame synchronisation happens using unique tokens in the data.

So there are 2 signals coming into the FPGA :

• EXT_CLK : in my case a few megahz
• DIN : data synchronous to the EXT_CLK
  

After sync and deserialisation, data is written into a FIFO, for consumption by a processor.

I currently see 2 design strategies, and I'd like your opinion / advice / feedback on choosing between them, or even a 3rd strategy if there would be a better one. Feel free to comment to some or all questions.

strategy 1 : CDC using async FIFO


basically the entire serial receive system (FSM + serial shift reg) is implemented in the 'external clock domain'. A dual domain FIFO takes care of the clock domain crossing.

Q1 : in my application, EXT_CLK can be disconnected / reconnected in irregular fashion, with temporary 'glitches' on the EXT_CLK input → can this put the FSM into an unknown state when using this strategy?
strategy 2 : CDC on the input CLK and data

In this strategy, the incoming EXT_CLK and EXT_DIN are considered as asynchronous inputs.

They are clock domain crossed to the internal FPGA clock domain (FPGA_CLK) using a 'CDC single'. The CDC of the clock is followed by an edge detector, which generates a single tick (width = 1 FPGA_CLK period) on a rising edge.

Once after the CDC's, the FSM, shift reg and both sides of the FIFO all work on the same clock domain.



Q2 : FPGA clock should be (a factor) higher than EXT_CLK_IN for this to work, is there some 'rule' that says it should be at least 4x, 8x, ... ?

Q3 : as an immediate conclusion to that, strategy 1 can probably run at a higher EXT_CLK frequency than strategy 2? Is that a reason why most designs on the web use strategy 1?

Q4: if I browse on the web and look at SPI slave implementations (couldn't find many HDLC implementations, and SPI slave comes close to this), I mostly see the first strategy implemented. However, this strategy of putting the CDC single on the input signals seems to be more rigid to me, especially when EXT_CLK could be disconnected/reconnected randomly. Or am I missing something here?

Q5 : I think another advantage of strategy 2 is that the FSM could transit multiple states during a single EXT_CLK cycle, hence having more 'flexibility' in FSM implementation.

Q6 : it looks like strategy 2 might use higher power than strategy 1, is that correct?

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