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我有一个用于Spartan-3(带有Opal Kelly XEM3001板)的项目,并尝试将其移植到Spartan-6(Opal Kelly XEM6001)。 大多数事情似乎都有效,除了这部分的PlanAhead / NgdBuild扼流圈: BUFGDLL clkbuf(.I(hi_in [0]),. O(ti_clk)); 因为在Spartan-6中似乎没有支持BUFGDLL,而且正如我所看到的,它在Spartan-3时甚至已经过时,发现一些手册说它被DCM_SP + BUFG的组合所取代。 怎么做,我怎么能改变这个代码是最新的(实际编译)? 谢谢! 以上来自于谷歌翻译 以下为原文 Hi! I have project that was used with a Spartan-3 (with an Opal Kelly XEM3001 board), and trying to port it to a Spartan-6 (Opal Kelly XEM6001). Most of the things seem to work, except PlanAhead/NgdBuild chokes on this part: BUFGDLL clkbuf(.I(hi_in[0]), .O(ti_clk)); since BUFGDLL is not seem to be supported in Spartan-6, and as I looked, it was even obsolete at Spartan-3 times, found some manual that says it is replaced by a combo of DCM_SP + BUFG. How's that done, how could I change this code to be up to date (and actually compile)? Thanks! |
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BUFGDLL从未存在过 - 它始终是特定配置中DLL和BUFG的简写。
真正的联系是: - 时钟在时钟引脚上进入FPGA - 时钟通过输入缓冲区(IBUFG) - IBUFG的输出转到DCM的CLKIN - DCM的CLK0输出进入BUFG - BUFG输出是用于设计的缓冲时钟(BUFGDLL的输出) - BUFG输出也进入DCM的CLKFB输入 构建它的最简单方法是使用CoreGen的Clocking Wizard。 它将实例化所有单元并为您连接所有信号。 Avrum 以上来自于谷歌翻译 以下为原文 A BUFGDLL never existed - it was always a shorthand for a DLL and a BUFG in a particular configuration. The real connection is: - clock comes into the FPGA on a clock capable pin - clock goes through an input buffer (IBUFG) - output of IBUFG goes to CLKIN of DCM - CLK0 output of DCM goes to BUFG - BUFG output is the buffered clock used for your design (the output of the BUFGDLL) - BUFG output also goes to the CLKFB input of the DCM The easiest way to build this is to use the Clocking Wizard from CoreGen. It will instantiate all the cells and connect all the signals for you. Avrum |
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