SARADC的输入阻抗

谢谢你的及时回复，Gyan。
在过去的几个月里，我一直在通过不同的渠道向塞浦路斯提同样的问题，但是我收到了类似的不正确的信息。
我认为这是一个非常简单的问题，但看来我要得到正确的答案更详细的解释我试过。
我知道模拟通道电阻在路由路径和采样速度限制的RC滤波效果的影响和对编程的一部分是完全可以理解的。
我问什么是4位数的PSoC可输入阻抗为我在我原来的邮件中说。
根据psoc5 adcsar分量表（柏大夫001-96049 REC C）和PSoC delta-sigma ADC ver3.30分量表（002-22359启**），典型的ADC的输入阻抗是180k欧姆和74k / 148k欧姆分别。
在PSoC 4位数V2.50成分表（002-19123启**），输入电阻是指定为2.2k欧姆最大。
即使它是定义为输入电阻（不是路径电阻）ADC的规格和规格没有其他路径的电阻的定义，我不能相信的价值因为这样低的ADC的输入阻抗会破坏sarmux功能/功能以来，几乎所有的应用程序将需要运算放大器缓冲器以减少负载效应由低的ADC输入阻抗连接到测量点引起的测量点。
如果这个值是真实的，所有复杂的计算和期望比0.01degc温度测量的想法我的应用笔记an66477是错的即使差分偏移校准和精确的电流源的管理控制。
但我得到的答案是相同的每次（2.2k欧姆），我不得不使用运算放大器和模拟多路复用器的设计我的系统，但是有一个问题，在PSoC Creator的模拟多路复用器（我将在单独的线程中，都有这个问题）所以我花了很多时间来实现模拟多路复用器函数T通过直接登记控制由于模拟多路复用器的问题。
由于程序很复杂，11模拟输入信号和都高于规定的控制，我只是试图通过测量电压与不同的源阻抗之前，我决定放弃这一部分对于我的应用程序发现阻抗很高检查ADC的输入阻抗她比2.2K欧姆。
现在我想柏确认PSoC 4位数的实际输入阻抗和更新数据表正确。
如果我可以，我希望柏队多付出一些关注的用户，我们可以避免寻找周围的工作，没有多余的时间提出的技术问题。
当做，
KH
                    
                    
               
                                                                                      以下为原文
                                            Thanks for the prompt reply, Gyan.
 
I've been asking the same question to Cypress in last few months through the different channel but have received the similar incorrect information.
I thought it was a very simple question but it seems that I have to explain more detail to get the correct answer - I tried before.
 
I know the Analog path resistance over the routing path and the sampling speed limitation caused by the R-C filtering effect and it's quite understandable for the programmable part.
 
What I asked was the input impedance of the PSoC 4 BLE SARADC input as I stated in my original email.
According to the PSoC5 ADCSAR component datasheet (Cypress doc 001-96049 Rec C) and the PSoC Delta-Sigma ADC Ver3.30 component datasheet (002-22359 REV**), the typical ADC input impedance is 180K Ohm and 74K/148K Ohm respectively.
In the PSoC 4 SARADC V2.50 component datasheet (002-19123 Rev**), the input resistance is specified as 2.2K Ohm max.
 
Even though it's defined as the input resistance (not the path resistance) of the ADC spec and no other path resistance definition in the spec, I couldn't believe the value since this low ADC input impedance would undermine the SARMUX function/feature since almost all the application will need the OP-AMP buffer to minimize the loading effect to the measurement point caused by the low ADC input impedance connected to the measurement point.
 
If this value is true, all the fancy calculations and the expectation of better than 0.01degC temp measurement idea i the App note AN66477 will be wrong even though the differential offset calibration and the accurate current source management control.
 
But the answers I got was the same each time (2.2K Ohm), I had to design my system using the OP-AMP and the Analog MUX but there was another issue with the Analog Mux in the PSoC Creator (I'll have this issue in the separate thread.) so I've spent lots of time to implement the Analog Mux function through the direct Register control - because of the Analog Mux issue.
 
Since the program got really complicated to control 11 Analog input signals and the both iDACs, I just tried to check the ADC input impedance by measuring the voltage with the different source impedance before I decide to give up this part for my application and found that the impedance is much higher than 2.2K Ohm.
 
Now I want Cypress to confirm the actual input impedance of the PSoC 4 SARADC and update the datasheet properly.
And if I may, I hope Cypress team to pay some more attention to the tech issues brought up by the user so that we can avoid the unnecessary time to find the work around for nothing.
 
Regards,
 
KH

你好，USER50501329，
2.2 K欧姆是电阻的路径（你可以看到文件，我共享）而不是ADC的输入阻抗。ADC的输入阻抗将是非常高的决定性的。但是，像你说的，在psoc4 ADC组件数据表没有提到它。
-吉安
                    
                    
               
                                                                                      以下为原文
                                            Hello user_508813299 ,
 
   The 2.2 K Ohm is the path resistance only ( You can see in the document, I shared ) and not the input impedance of the ADC. The input impedance of ADC  will be very high definitively. However, as you explained , it is not mentioned in the PSoC4 ADC Component datasheet.
 
-Gyan

您好!
数据表值仅指定路由电阻。实际的输入阻抗，你看从ADC会高于这个。这是路由电阻，直到采样电容器。由于采样电容器的实际性能将有大约1/3（采样率* 6.4pf）。
最佳问候
                    
                    
               
                                                                                      以下为原文
                                            Hi
 
The datasheet value specifies only the routing resistance. The actual input impedance you see from the ADC will be higher than this. It is the routing resistance till the sampling capacitor. The actual resistance due to the sampling capacitor will be some where around  1/(sample rate * 6.4pF).
 
 
Best Regards,
VSRS